M50FW040K1 STMicroelectronics, M50FW040K1 Datasheet - Page 9

• Manufacturer Part Number: M50FW040K1
• Description: Flash 3.6V 4M (512Kx8)
• Manufacturer: STMicroelectronics

Specifications of M50FW040K1

• Data Bus Width: 8 bit
• Memory Type: NOR
• Memory Size: 4 Mbit
• Architecture: Sectored
• Interface Type: Firmware Hub
• Access Time: 11 ns, 50 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 20 mA
• Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: PLCC-32
• Organization: 512 KB x 8
• Lead Free Status / Rohs Status: No

SIGNAL DESCRIPTIONS
There are two different bus interfaces available on
this part. The active interface is selected before
power-up or during Reset using the Interface Con-
figuration Pin, IC.
The signals for each interface are discussed in the
Firmware Hub (FWH) Signal Descriptions
and the
Signal Descriptions
nals are discussed in the
tions
Firmware Hub (FWH) Signal Descriptions
For the Firmware Hub (FWH) Interface see
2., Logic Diagram (FWH
1., Signal Names (FWH
Input/Output Communications (FWH0-FWH3). All
Input and Output Communication with the memory
take place on these pins. Addresses and Data for
Bus Read and Bus Write operations are encoded
on these pins.
Input Communication Frame (FWH4). The In-
put Communication Frame (FWH4) signals the
start of a bus operation. When Input Communica-
tion Frame is Low, V
Clock a new bus operation is initiated. If Input
Communication Frame is Low, V
operation then the operation is aborted. When In-
put Communication Frame is High, V
rent bus operation is proceeding or the bus is idle.
Identification Inputs (ID0-ID3). The
tion Inputs select the address that the memory re-
sponds to. Up to 16 memories can be addressed
on a bus. For an address bit to be ‘0’ the pin can
be left floating or driven Low, V
down resistor is included with a value of R
an address bit to be ‘1’ the pin must be driven
High, V
through each pin when pulled to V
By convention the boot memory must have ad-
dress ‘0000’ and all additional memories take se-
quential addresses starting from ‘0001’.
General Purpose Inputs (FGPI0-FGPI4). The Gen-
eral Purpose Inputs can be used as digital inputs
for the CPU to read. The General Purpose Inputs
Register holds the values on these pins. The pins
must have stable data from before the start of the
cycle that reads the General Purpose Input Regis-
ter until after the cycle is complete. These pins
must not be left to float, they should be driven Low,
V
Interface Configuration (IC). The Interface Con-
figuration input selects whether the Firmware Hub
(FWH) or the Address/Address Multiplexed (A/A
Mux) Interface is used. The chosen interface must
be selected before power-up or during a Reset
and, thereafter, cannot be changed. The state of
IL,
or High, V
section below.
IH
Address/Address Multiplexed (A/A Mux)
; there will be a leakage current of I
IH
.
section below. The supply sig-
IL
, on the rising edge of the
Interface).
Supply Signal Descrip-
Interface), and
IL
; an internal pull-
IH
IL
, during a bus
; see
IH
Identifica-
, the cur-
Table 18.
section
Figure
IL
Table
. For
LI2
the Interface Configuration, IC, should not be
changed during operation.
To select the Firmware Hub (FWH) Interface the
Interface Configuration pin should be left to float or
driven Low, V
Multiplexed (A/A Mux) Interface the pin should be
driven High, V
included with a value of R
current of I
see
Interface Reset (RP). The Interface Reset (RP)
input is used to reset the memory. When Interface
Reset (RP) is set Low, V
mode: the outputs are put to high impedance and
the current consumption is minimized. When RP is
set High, V
After exiting Reset mode, the memory enters
Read mode.
CPU Reset (INIT). The CPU Reset, INIT, pin is
used to Reset the memory when the CPU is reset.
It behaves identically to Interface Reset, RP, and
the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
Clock (CLK). The Clock, CLK, input is used to
clock the signals in and out of the Input/Output
Communication Pins, FWH0-FWH3. The Clock
conforms to the PCI specification.
Top Block Lock (TBL). The Top Block Lock in-
put is used to prevent the Top Block (Block 7) from
being changed. When Top Block Lock, TBL, is set
Low, V
Top Block have no effect, regardless of the state
of the Lock Register. When Top Block Lock, TBL,
is set High, V
termined by the Lock Register. The state of Top
Block Lock, TBL, does not affect the protection of
the Main Blocks (Blocks 0 to 6).
Top Block Lock, TBL, must be set prior to a Pro-
gram or Erase operation is initiated and must not
be changed until the operation completes or un-
predictable results may occur. Care should be tak-
en to avoid unpredictable behavior by changing
TBL during Program or Erase Suspend.
Write Protect (WP). The Write Protect input is
used to prevent the Main Blocks (Blocks 0 to 6)
from being changed. When Write Protect, WP, is
set Low, V
Main Blocks have no effect, regardless of the state
of the Lock Register. When Write Protect, WP, is
set High, V
mined by the Lock Register. The state of Write
Protect, WP, does not affect the protection of the
Top Block (Block 7).
Write Protect, WP, must be set prior to a Program
or Erase operation is initiated and must not be
changed until the operation completes or unpre-
Table 18.
IL
, Program and Erase operations in the
IL
LI2
IH
IH
, Program and Erase operations in the
, the memory is in normal operation.
, the protection of the Block deter-
through each pin when pulled to V
IH
IH
IL
, the protection of the Block is de-
; to select the Address/Address
. An internal pull-down resistor is
IL
IL
, the memory is in Reset
; there will be a leakage
M50FW040
9/41
IH
;