PCA9559PW NXP Semiconductors, PCA9559PW Datasheet - Page 2

• Manufacturer Part Number: PCA9559PW
• Description: EEPROM 5BIT MUX/1BIT LATCH 6-BIT DIPSW
• Manufacturer: NXP Semiconductors

Specifications of PCA9559PW

• Interface Type: I2C
• Maximum Clock Frequency: 400 KHz
• Access Time: 10 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 100 uA
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-360
• Minimum Operating Temperature: 0 C
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature: 0 C to + 70 C
• Lead Free Status / Rohs Status: Details
• Other names: PCA9559PW,112

Philips Semiconductors
FEATURES
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DESCRIPTION
The PCA9559 is a 20-pin CMOS device consisting of one 6-bit
non-volatile EEPROM registers, 5 hardware pin inputs and a 5-bit
multiplexed output with one latched EEPROM bit. It is used for DIP
switch-free or jumper-less system configuration and supports Mobile
and Desktop VID Configuration, where 2 preset values (1 set of
internal non-volatile registers and 1 set of external hardware pins)
set processor voltage for operation in either performance or deep
sleep modes. The PCA9559 is also useful in server and
telecom/networking applications when used to replace DIP switches
or jumpers, since the settings can be easily changed via I
without having to power down the equipment to open the cabinet.
The non-volatile memory retains the most current setting selected
before the power is turned off.
The PCA9559 typically resides between the CPU and Voltage
Regulator Module (VRM) when used for CPU VID (Voltage
IDentification code) configuration. It is used to bypass the
CPU-defined VID values and provide a different set of VID values to
the VRM, if an increase in the CPU voltage is desired. An increase
in CPU voltage combined with an increase in CPU frequency leads
to a performance boost of up to 7.5%. Lower CPU voltage reduces
power consumption.
The PCA9559 has 2 address pins allowing up to 4 devices to be
placed on the same I
ORDERING INFORMATION
Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.
2003 Jun 27
5-bit 2-to-1 multiplexer, 1-bit latch DIP switch
6-bit internal non-volatile register
Internal non-volatile register programmable and readable via
I
Override input forces all outputs to logic 0
5 open drain multiplexed outputs
1 open drain non-multiplexed (latched) output
5 V and 2.5 V tolerant inputs
Useful for ‘jumperless’ configuration of PC motherboards
2 address pins, allowing up to 4 devices on the I
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
5-bit multiplexed/1-bit latched 6-bit
I
2
20-Pin Plastic TSSOP
C-bus
2
C EEPROM DIP switch
PACKAGES
2
C-bus or SMBus.
TEMPERATURE RANGE
0 to +70 °C
2
C-bus
2
C/SMBus
ORDER CODE
PCA9559PW
2
PIN CONFIGURATION
PIN DESCRIPTION
12-16
NUM-
BER
PIN
5-9
10
17
18
19
20
11
1
2
3
4
MUX_OUT E-A
NON_MUXED_
MUX_SELECT
OVERRIDE_N
MUX_IN A-E
A1 Address
A0 Address
MUX_IN D
MUX_IN A
MUX_IN B
MUX_IN C
MUX_IN E
SYMBOL
I
I
TOPSIDE MARK
2
I
2
I
2
2
C SDA
C SCL
GND
C SDA
OUT
C SCL
V
WP
GND
Figure 1. Pin configuration
CC
PCA9559
A0
A1
10
1
2
3
4
5
6
7
8
9
Serial I
Serial bi-directional I
A1
A0
External inputs to multiplexer
Ground
Selects MUX_IN inputs or register
contents for MUX_OUT outputs
Open drain multiplexed outputs
Open drain outputs from
non-volatile memory
Forces all outputs to logic 0
Non-volatile register write-protect
Power supply: +3.0 to +3.6 V
2
20
19
18
17
16
15
14
13
12
11
C-bus clock
V
WP
OVERRIDE_N
NON_MUXED_OUT
MUX_OUT A
MUX_OUT B
MUX_OUT C
MUX_OUT D
MUX_OUT E
MUX_SELECT
DRAWING NUMBER
CC
SW00216
FUNCTION
SOT360-1
PCA9559
2
C-bus data
Product data