CY7C43642AV-10AC Cypress Semiconductor Corp, CY7C43642AV-10AC Datasheet - Page 13

• Manufacturer Part Number: CY7C43642AV-10AC
• Description: FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 x 2 120-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C43642AV-10AC

• Package: 120TQFP
• Configuration: Dual
• Bus Directional: Bi-Directional
• Density: 72 Kb
• Organization: 1Kx36x2
• Data Bus Width: 36 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: 0 to 70 °C

Document #: 38-06020 Rev. *C
Switching Waveforms
Notes:
22. Reset is performed in the same manner for FIFO2 to load X2 and Y2 with a preset value.
23. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles. FIFO can only be programmed in parallel
24. t
Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
(CY Standard and FWFT Modes)
FWFT/STAN
CLKA
MRST1, MRST2
FS1, FS0
FFA/IRA
ENA
A
CLKB
FFB/IRB
MRST1
FS1, FS0
FFA/IRA
EFB/ORB
AEB
AFA
CLKA
CLKB
MBF1
FIFO1 Reset Loading X1 and Y1 with a Preset Value of Eight
0 35
when FFA/IRA is HIGH.
edge of CLKA and rising edge of CLKB is less than t
SKEW1
is the minimum time between the rising CLKA edge and a rising CLKB for FFB/IRB to transition HIGH in the next cycle. If the time between the rising
t
FSS
t
FSH
t
RSTS
[23]
t
t
RSF
t
t
RSF
t
RSF
RSF
RSF
SKEW1
t
WFF
AFA Offset (Y1)
, then FFB/IRB may transition HIGH one cycle later than shown.
t
DS
t
DH
AEB Offset (X1)
t
t
ENS
FSS
[22]
t
t
ENH
RSTH
t
FSH
AFB Offset (Y2)
t
FWS
AEA Offset (X2)
t
WFF
t
SKEW1
CY7C43642AV
CY7C43662AV
CY7C43682AV
First Word to FIFO1
[24]
Page 13 of 30
t
WFF