CY7C43642AV-10AC Cypress Semiconductor Corp, CY7C43642AV-10AC Datasheet - Page 16

• Manufacturer Part Number: CY7C43642AV-10AC
• Description: FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 x 2 120-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C43642AV-10AC

• Package: 120TQFP
• Configuration: Dual
• Bus Directional: Bi-Directional
• Density: 72 Kb
• Organization: 1Kx36x2
• Data Bus Width: 36 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: 0 to 70 °C

Document #: 38-06020 Rev. *C
Switching Waveforms
Note:
31. t
ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
CLKA
MBA
ENA
A
CLKB
CSB
W/RB
ENB
B
CSA
W/RA
FFA/IRA
EFB/ORB
MBB
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than t
of the first word to the output register may occur one CLKB cycle later than shown.
SKEW1
0–35
0–35
is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output
HIGH
LOW
HIGH
HIGH
LOW
LOW
FIFO1 Empty
(continued)
t
t
t
ENS
DS
ENS
W1
Old Data in FIFO1 Output Register
t
t
t
ENH
ENH
DH
t
SKEW1
[31]
t
CLKH
t
CLK
t
CLKL
t
CLKH
t
CLK
t
CLKL
t
t
A
REF
t
ENS
t
SKEW1
ENH
t
REF
, then the transition of ORB HIGH and load
W1
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