CY7C43642AV-10AC Cypress Semiconductor Corp, CY7C43642AV-10AC Datasheet - Page 3

• Manufacturer Part Number: CY7C43642AV-10AC
• Description: FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 x 2 120-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C43642AV-10AC

• Package: 120TQFP
• Configuration: Dual
• Bus Directional: Bi-Directional
• Density: 72 Kb
• Organization: 1Kx36x2
• Data Bus Width: 36 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: 0 to 70 °C

Document #: 38-06020 Rev. *C
Functional Description
The CY7C436X2AV is a monolithic, high-speed, low-power,
CMOS Bidirectional Synchronous FIFO memory that supports
clock frequencies up to 133 MHz and has Read access times
as fast as 6 ns. Two independent 1K/4K/16K × 36 dual-port
SRAM FIFOs on board each chip buffer data in opposite direc-
tions.
The CY7C436X2AV is a synchronous (clocked) FIFO,
meaning that each port employs a synchronous interface. All
data transfers through a port are gated to the LOW-to-HIGH
transition of a port clock by enable signals. The clocks for each
port are independent of one another and can be asynchronous
or coincident. The enables for each port are arranged to
provide a simple bidirectional interface between micropro-
cessors and/or buses with synchronous control.
Communication between each port may bypass the FIFOs via
two mailbox registers. The mailbox registers’ width matches
the selected Port B bus width. Each mailbox register has a flag
(MBF1 and MBF2) to signal when new mail has been stored.
Master Reset initializes the Read and Write pointers to the first
location of the memory array, and selects parallel flag
programming, or one of the three possible default flag offset
settings, 8, 16, or 64. Each FIFO has its own independent
Master Reset pin, MRST1 and MRST2.
The CY7C436X2AV has two modes of operation. In CY
Standard mode, the first word written to an empty FIFO is
deposited into the memory array. A Read operation is required
to access that word (along with all other words residing in
memory). In the First-Word Fall-Through mode (FWFT), the
first word (36-bit wide) written to an empty FIFO appears
automatically on the outputs, no Read operation required
(nevertheless, accessing subsequent words does necessitate
a formal Read request). The state of the FWFT/STAN pin
during FIFO operation determines the mode in use.
Pin Definitions
A
AEA
AEB
AFA
AFB
B
FWFT/STAN
Note:
Signal Name
1.
0–35
0–35
When FIFO is operated at the almost empty/full boundary, there may be an uncertainty of up to two clock cycles for flag deassertion, but the flag will always
be asserted exactly when the FIFO content reaches the programmed value. Use the assertion edge for trigger if flag accuracy is required. Refer to the Cypress
application note entitled “Designing with CY7C436xx Synchronous FIFOs” for more details on flag uncertainties.
Port A Data
Port A Almost
Empty Flag
Port B Almost
Empty Flag
Port A Almost
Full Flag
Port B Almost
Full Flag
Port B Data
First-Word
Fall-Through /
CY Standard
Select
Description
I/O
I/O 36-bit bidirectional data port for side A.
I/O 36-bit bidirectional data port for side B.
O Programmable Almost Empty flag synchronized to CLKA. It is LOW when the
O Programmable Almost Empty flag synchronized to CLKB. It is LOW when the
O Programmable Almost Full flag synchronized to CLKA. It is LOW when the number
O Programmable Almost Full flag synchronized to CLKB. It is LOW when the number
I
number of words in FIFO2 is less than or equal to the value in the Almost Empty A offset
register, X2.
number of words in FIFO1 is less than or equal to the value in the Almost Empty B offset
register, X1.
of empty locations in FIFO1 is less than or equal to the value in the Almost Full A offset
register, Y1.
of empty locations in FIFO2 is less than or equal to the value in the Almost Full B offset
register, Y2.
During Master Reset. A HIGH on FWFT selects CY Standard mode, a LOW selects
First -Word Fall-Through mode. Once the timing mode has been selected, the level on
FWFT/STAN must be static throughout device operation.
[1]
[1]
[1]
[1]
Each FIFO has a combined Empty/Output Ready flag
(EFA/ORA and EFB/ORB) and a combined Full/Input Ready
flag (FFA/IRA and FFB/IRB). The EF and FF functions are
selected in the CY Standard mode. EF indicates whether the
memory is full or not. FF indicates whether the FIFO is full. The
IR and OR functions are selected in the First- Word
Fall-Through mode. IR indicates whether or not the FIFO has
available memory locations. OR shows whether the FIFO has
data available for reading or not. It marks the presence of valid
data on the outputs.
Each FIFO has a programmable Almost Empty flag (AEA and
AEB) and a programmable Almost Full flag (AFA and AFB).
AEA and AEB indicate when a selected number of words
written to FIFO memory achieve a predetermined “almost
empty state.” AFA and AFB indicate when a selected number
of words written to the memory achieves a predetermined
“almost full state.”
FFA/IRA, FFB/IRB, AFA, and AFB are synchronized to the port
clock that writes data into its array. EFA/ORA, EFB/ORB, AEA,
and AEB are synchronized to the port clock that reads data
from its array. Programmable offset for AEA, AEB, AFA, and
AFB are loaded in parallel using Port A. Three default offset
settings are also provided. The AEA and AEB threshold can
be set at 8, 16, or 64 locations from the empty boundary and
AFA and AFB threshold can be set at 8, 16, or 64 locations
from the full boundary. All these choices are made using the
FS0 and FS1 inputs during Master Reset.
Two or more devices may be used in parallel to create wider
data paths.
The CY7C436X2AV FIFOs are characterized for operation
from 0°C – 70°C commercial, and from –40°C – 85°C indus-
trial. Input ESD protection is greater than 2001V, and latch-up
is prevented by the use of guard rings.
Function
[1]
CY7C43642AV
CY7C43662AV
CY7C43682AV
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