P89LV51RD2BBC NXP Semiconductors, P89LV51RD2BBC Datasheet - Page 42

• Manufacturer Part Number: P89LV51RD2BBC
• Description: MCU 8-Bit 89LV 80C51 CISC 64KB Flash 3.3V 44-Pin TQFP Tray
• Manufacturer: NXP Semiconductors

Specifications of P89LV51RD2BBC

• Package: 44TQFP
• Device Core: 80C51
• Family Name: 89LV
• Maximum Speed: 40 MHz
• Ram Size: 1 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 32
• Interface Type: SPI/UART
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 3

NXP Semiconductors
P89LV51RB2_RC2_RD2_5
Product data sheet
6.7.1 SPI features
6.7.2 SPI description
6.7 SPI
In a more complex system the following could be used to select slaves 1 and 2 while
excluding slave 0:
Example 1, slave 0:
Example 2, slave 1:
Example 3, slave 2:
In the above example the differentiation among the 3 slaves is in the lower 3 address bits.
Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1
requires that bit 1 = 0 and it can be uniquely addressed by 1110 0101. Slave 2 requires
that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude
Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2.
The Broadcast Address for each slave is created by taking the logical OR of SADDR and
SADEN. Zeros in this result are treated as don’t-cares. In most cases, interpreting the
don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR
and SADEN are loaded with 0s. This produces a given address of all ‘don’t cares’ as well
as a Broadcast address of all ‘don’t cares'. This effectively disables the Automatic
Addressing mode and allows the microcontroller to use standard UART drivers which do
not make use of this feature.
The SPI allows high-speed synchronous data transfer between the
P89LV51RB2/RC2/RD2 and peripheral devices or between several
P89LV51RB2/RC2/RD2 devices.
SADDR = 1100 0000
--------------------------------------------------- -
SADDR = 1110 0000
--------------------------------------------------- -
SADDR = 1100 0000
--------------------------------------------------- -
SADEN = 1111 1001
SADEN = 1111 1010
SADEN = 1111 1100
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Given = 1100 0XX0
Given = 1110 0X0X
Given = 1100 00XX
Master or slave operation
10 MHz bit frequency (maximum)
LSB first or MSB first data transfer
Four programmable bit rates
End of transmission (SPIF)
Write collision flag protection (WCOL)
Wake-up from Idle mode (slave mode only)
Rev. 05 — 15 December 2009
Figure 16
P89LV51RB2/RC2/RD2
shows the correspondence between master
8-bit microcontrollers with 80C51 core
© NXP B.V. 2009. All rights reserved.
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