GS840E18AT-166 GSI TECHNOLOGY, GS840E18AT-166 Datasheet

GS840E18AT-166

Manufacturer Part Number

GS840E18AT-166

Description

SRAM Chip Sync Dual 3.3V 4M-Bit 256K x 18 8.5ns/3.5ns 100-Pin TQFP Tray

Manufacturer

GSI TECHNOLOGY

Datasheet

1.GS840E18AT-166.pdf (31 pages)

Specifications of GS840E18AT-166

Package

100TQFP

Timing Type

Synchronous

Density

4 Mb

Data Rate Architecture

SDR

Typical Operating Supply Voltage

3.3 V

Number Of I/o Lines

18 Bit

Number Of Ports

Number Of Words

256K

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TQFP, BGA

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipelined

• Dual Cycle Deselect (DCD) operation

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipelined mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock control, registered, address, data, and control

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC standard 100-lead TQFP or 119-Bump BGA package

• Pb-Free 100-lead TQFP package available

Functional Description

Applications

The GS840E18/32/36A is a 4,718,592-bit (4,194,304-bit for

x32 version) high performance synchronous SRAM with a 2-

bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications ranging from DSP main store

to networking chip set support. The GS84018/32/36A is

available in a JEDEC standard 100-lead TQFP or 119-Bump

BGA package.

Controls

Addresses, data I/Os, chip enables (E

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

Rev: 1.12 10/2004

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

operation

Through

Pipeline

3-1-1-1

2-1-1-1

Flow

, E

256K x 18, 128K x 32, 128K x 36

, E

4Mb Sync Burst SRAMs

tCycle

), address burst

370 mA

245 mA

5.3 ns

3.0 ns

7.5 ns

8.5 ns

Parameter Synopsis

–190

1/31

335 mA

210 mA

5.5 ns

3.0 ns

–180

8 ns

9 ns

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin/bump (pin 14 in the TQFP and

bump 5R in the BGA). Holding the FT mode pin/bump low

places the RAM in Flow Through mode, causing output data to

bypass the Data Output Register. Holding FT high places the

RAM in Pipelined mode, activating the rising-edge-triggered

Data Output Register.

DCD Pipelined Reads

The GS840E18/32/36A is a DCD (Dual Cycle Deselect)

pipelined synchronous SRAM. SCD (Single Cycle Deselect)

versions are also available. DCD SRAMs pipeline disable

commands to the same degree as read commands. DCD RAMs

hold the deselect command for one full cycle and then begin

turning off their outputs just after the second rising edge of

clock.

Byte Write and Global Write

Byte write operation is performed by using byte write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS840E18/32/36A operates on a 3.3 V power supply and

all inputs/outputs are 3.3 V- and 2.5 V-compatible. Separate

output power (V

from the internal circuit.

310 mA

190 mA

6.0 ns

3.5 ns

8.5 ns

10 ns

–166

GS840E18/32/36AT/B-190/180/166/150/100

280 mA

165 mA

6.6 ns

3.8 ns

10 ns

12 ns

–150

DDQ

) pins are used to de-couple output noise

190 mA

135 mA

4.5 ns

10 ns

12 ns

15 ns

–100

3.3 V and 2.5 V I/O

190 MHz–100 MHz

3.3 V V

Related parts for GS840E18AT-166

GS840E18AT-166 Summary of contents

Page 1

... KQ I 370 mA 335 mA 310 7 8 tCycle 8 245 mA 210 mA 190 mA DD 1/31 190 MHz–100 MHz 3.3 V and 2.5 V I/O ) pins are used to de-couple output noise DDQ –150 –100 6 3.8 ns 4.5 ns 280 mA 190 165 mA 135 mA © 1999, GSI Technology 3 ...

Page 2

... V 11 DDQ DDQ DQP DDQ Rev: 1.12 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840E18/32/36AT/B-190/180/166/150/100 GS840E18A 100-Pin TQFP Pinout (Package T) 256K x 18 Top View 2/ DDQ DQP VDDQ VDD VDDQ VDDQ © 1999, GSI Technology ...

Page 3

... DDQ DDQ DDQ DDQ Rev: 1.12 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840E18/32/36AT/B-190/180/166/150/100 GS840E32A 100-Pin TQFP Pinout (Package T) 128K x 32 Top View 3/ DDQ DDQ DDQ DDQ © 1999, GSI Technology ...

Page 4

... V 27 DDQ DQP Rev: 1.12 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840E18/32/36AT/B-190/180/166/150/100 GS840E36A 100-Pin TQFP Pinout (Package T) 128K x 36 Top View 4/31 DQP DDQ DDQ DDQ DDQ DQP 51 A © 1999, GSI Technology ...

Page 5

... Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply No Connect 5/31 © 1999, GSI Technology ...

Page 6

... GS840E18A Pad Out—119-Bump BGA—Top View (Package Rev: 1.12 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840E18/32/36AT/B-190/180/166/150/100 ADSP DDQ ADSC DDQ ADV DDQ DDQ DQP LBO DDQ 6/ DDQ DQP DDQ DDQ DDQ DDQ © 1999, GSI Technology ...

Page 7

... GS840E32A Pad Out—119-Bump BGA—Top View (Package Rev: 1.12 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840E18/32/36AT/B-190/180/166/150/100 ADSP DDQ NC A ADSC DDQ ADV DDQ DDQ LBO DDQ 7/ DDQ DDQ DDQ DDQ DDQ © 1999, GSI Technology ...

Page 8

... T U Rev: 1.12 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840E18/32/36AT/B-190/180/166/150/100 ADSP DDQ NC A ADSC DQP DDQ ADV DDQ DDQ DQP LBO DDQ 8/ DDQ DQP DDQ DDQ DDQ DQP DDQ © 1999, GSI Technology ...

Page 9

Page 10

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840E18/32/36AT/B-190/180/166/150/100 GS840E18/32/36A Block Diagram Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register 10/31 A Memory Array DQx0–DQx9 © 1999, GSI Technology ...

Page 11

... LBO Interleaved Burst L Flow Through Pipeline Active ZZ Standby Interleaved Burst Sequence 10 11 1st address 11 00 2nd address 00 01 3rd address 01 10 4th address Note: The burst counter wraps to initial state on the 5th clock. 11/ A[1:0] A[1:0] A[1:0] A[1: © 1999, GSI Technology ...

Page 12

... C D Rev: 1.12 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840E18/32/36AT/B-190/180/166/150/100 may be used in any combination with BW to write single or multiple bytes. D 12/ Notes © 1999, GSI Technology ...

Page 13

... Rev: 1.12 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840E18/32/36AT/B-190/180/166/150/100 State Diagram Key None X H None X L None Next CR X Next CR H Next CW X Next 13/31 2 ADSP ADSC ADV © 1999, GSI Technology High-Z X High-Z X High ...

Page 14

... ADSP is tied high and ADV is tied low. Rev: 1.12 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840E18/32/36AT/B-190/180/166/150/100 Simplified State Diagram X Deselect First Write Burst Write 14/ First Read Burst Read and Write ( and GW) control inputs © 1999, GSI Technology ...

Page 15

... Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.12 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840E18/32/36AT/B-190/180/166/150/100 Simplified State Diagram with G X Deselect First Write Burst Write 15/ First Read Burst Read CR © 1999, GSI Technology ...

Page 16

Page 17

... This parameter is sample tested. Rev: 1.12 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840E18/32/36AT/B-190/180/166/150/100 Overshoot Measurement and Timing V +-2. Symbol Test conditions 3 OUT OUT 17/31 20% tKC Typ. Max. Unit © 1999, GSI Technology ...

Page 18

... Output Disable OUT –4 mA –4 mA 18/31 Output Load 2 2.5 V 225Ω 225Ω 5pF Min – ≥ V – ≤ V – ≥ V –300 ≤ V –1uA IL IN – 2.375 V 1.7 V DDQ = 3.135 V 2.4 V DDQ © 1999, GSI Technology Max 1uA 1 uA 300 0.4 V ...

Page 19

... GSI Technology Unit ...

Page 20

... GSI Technology Unit ...

Page 21

... E2 and E3 only sampled with ADSP and ADSC tS tOHZ tH Q(A) D(B) 21/31 Read C+1 Read C+2 Read C+3 Cont Burst Read Burst Read Deselected with E1 E1 masks ADSP tKQ tLZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 1999, GSI Technology Deselect tKQX tHZ ...

Page 22

... Flow Through Mode Timing Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read tKQ tOHZ tLZ D(B) Q(C) 22/31 Cont Deselect Deselected with E1 tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 1999, GSI Technology tKQX ...

Page 23

... Rev: 1.12 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840E18/32/36AT/B-190/180/166/150/100 Sleep Mode Timing Diagram tKH tKH tKC tKC tKL tKL tZZS tZZH 23/31 tZZR © 1999, GSI Technology ...

Page 24

... PD LD Rev: 1.12 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840E18/32/36AT/B-190/180/166/150/100 0 Out (Pull Dow n) VDDQ - V Out (Pull Up 24/31 V DDQ I Out VOut V SS 2.5 3 3 © 1999, GSI Technology 4 ...

Page 25

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840E18/32/36AT/B-190/180/166/150/100 θ 0.10 0.15 1.40 1.45 0.30 0.40 0.20 — e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 — 7° 25/ © 1999, GSI Technology ...

Page 26

... Package Dimensions—119-Bump FPBGA (Package B, Variation 1 Pin #1 Corner 0.70 REF 12.00 SEATING PLANE C Rev: 1.12 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840E18/32/36AT/B-190/180/166/150/100 BOTTOM VIEW Ø0. Ø0. Ø0.60~0.90 (119x) Ø1.00(3x) REF 0.20(4x) 26/ 1.27 7.62 14±0.20 © 1999, GSI Technology ...

Page 27

... GS840E36AT-180 128K x 36 GS840E36AT-166 128K x 36 GS840E36AT-150 128K x 36 GS840E36AT-100 256K x 18 GS840E18AT-190I 256K x 18 GS840E18AT-180I 256K x 18 GS840E18AT-166I 256K x 18 GS840E18AT-150I 256K x 18 GS840E18AT-100I 128K x 32 GS840E32AT-190I 128K x 32 GS840E32AT-180I 128K x 32 GS840E32AT-166I 128K x 32 GS840E32AT-150I 128K x 32 ...

Page 28

... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.12 10/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 29

Page 30

... Documentation standards • Corrected typos in revision history table on page 31 • Reduced table on page 1 and Operating DD Content Currents table • Removed 200 MHz references from entire datasheet Content • Updated format Content • Added 190 MHz speed bin 30/31 © 1999, GSI Technology ...

Page 31

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS840E18/32/36AT/B-190/180/166/150/100 Page /Revisions;Reason • Updated entire format Content • Corrected current numbers to match NBT parts • Removed Preliminary banner • Added Pb-free TQFP information Content • Added variation number to 119 BGA information 31/31 © 1999, GSI Technology ...

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