FW82371EBSL37M Intel, FW82371EBSL37M Datasheet - Page 16

no-image

FW82371EBSL37M

Manufacturer Part Number
FW82371EBSL37M
Description
Embedded Processor 352-Pin BGA
Manufacturer
Intel
Datasheet

Specifications of FW82371EBSL37M

Package
352BGA
Intel
12.
13.
16
®
82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M
The DC Characteristics for SMI#, as specified in the 82371AB (PIIX4) PCI ISA IDE Xcelerator
Timing Specification datasheet addendum is changed from 7 mA @ 400 mV to 10mA @ 450 mV
to accommodate stronger external pull-up resistors.
This change applies to all steppings of the PIIX4/PIIX4E/PIIX4M and is planned to be
incorporated into the next revision of the 82371AB (PIIX4) PCI ISA IDE Xcelerator Timing
Specification datasheet addendum.
The throttle duty cycle bits (THTL_DTY) in the Processor Control Register (PCNTRL) are being
changed to match the ACPI specification.
This change applies to all steppings of the PIIX4E and PIIX4M and is planned to be incorporated
into the next revision of the datasheets.
7.2.7 PCNTRL —PROCESSOR CONTROL REGISTER (IO)
I/O Address:
Default Value:
Attribute
V
Manual Throttle Duty Cycle (PIIX4E and PIIX4M only)
OL
7:0
3:1
Bit
/I
OL
for SMI# Changes to 10 mA @ 450 mV
Not Implemented
Throttle Duty Programming Bits (THTL_DTY)—R/W. Selects the duty cycle of the STPCLK#
signal when the system is in the system throttling mode. The duty cycle indicates the percentage of
time the STPCLK# signal is asserted while in the throttle mode. The field is decoded as follows:
Bits[2:0]
000
001
010
011
Base + (10h)
00h
Read/Write
Mode
Reserved
87.5%
75%
62.5%
Bits[2:0]
100
101
110
111
Description
Mode
50%
37.5%
25%
12.5%
Specification Update
R

Related parts for FW82371EBSL37M