FW82371EBSL37M Intel, FW82371EBSL37M Datasheet - Page 47

• Manufacturer Part Number: FW82371EBSL37M
• Description: Embedded Processor 352-Pin BGA
• Manufacturer: Intel

Specifications of FW82371EBSL37M

• Package: 352BGA

21.
22.
Specification Update
R
SMI#. The system software can wait for an interrupt to signal completion or it can monitor the
SMBus Interrupt/Host Completion status bit. An interrupt is also signaled if an error occurred
during the transaction or if the transaction was terminated by software setting the KILL bit. The
SMBHSTCNT, SMBHSTCMD, SMBHSTADD, SMBHSTDAT0, SMBHSTDAT1, and
SMBBLKDAT registers should not be accessed after setting the START bit while the
HOST_BUSY bit is active until completion of the transaction as indicated by the SMBus
Interrupt/Host Completion status bit going active.
The SMBus controller will not respond to the START bit being set unless all interrupt status bits in
the SMBHSTSTS register have been cleared.
For Block Read or Block Write protocols, the data is stored in a 32-byte block data storage array.
This array is addressed via an internal index pointer. The index pointer is initialized to zero on
each read of the SMBHSTCNT register. After each access to the SMBBLKDAT register, the index
pointer is incremented by one. For Block Write transactions, the data to be transferred is stored in
this array and the byte count is stored in SMBHSTDAT0 register prior to initiating the transaction.
For Block Read transactions, the SMBus peripheral determines the amount of data transferred.
After the transaction completes, the byte count transferred is located in SMBHSTDAT0 register
and data is stored in the block data storage array. Accesses to the array during execution of the
SMBus transaction always start at address 0.
Any register values needed for computation purposes should be saved prior to the starting of a new
transaction, as the SMBus host controller updates the registers while executing the new transaction.
GPI14 for Device 5 Can Cause IO Trap SMI#
Page 219 of the datasheet, Section 11.3.5.6, Device 5 Floppy Disk Drive, describes how the PIIX4
will respond to GPI14 for Device 5 system events. The third bullet currently states “Assertion of
GPI14. The polarity of active signal (high or low) is selectable. This can cause idle, burst, or global
standby timer reloads.”
This bullet is changed to “Assertion of GPI14. The polarity of active signal (high or low) is
selectable. This can cause idle, burst, global standby timer reloads, or IO Trap SMI#.”
This clarification applies to all steppings of the PIIX4/PIIX4E/PIIX4M and is planned to be
incorporated into the next revision of the PIIX4 datasheet.
XDIR# Assertion
Page 22 of the datasheet, section 2.1.3, X-Bus Interface, describes the XDIR# signal. The second
sentence of the description, “XDIR# is asserted (driven low) for all I/O read cycles regardless if the
accesses is to a PIIX4 supported device.” should be changed to “XDIR# is asserted (driven low)
for all I/O read cycles targeting the XBUS or enabled Generic Decode Chip Selects.”
This clarification applies to all steppings of the PIIX4/PIIX4E/PIIX4M and is planned to be
incorporated into the next revision of the PIIX4 datasheet.
Intel
®
82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M
47