FW82371EBSL37M Intel, FW82371EBSL37M Datasheet - Page 30

• Manufacturer Part Number: FW82371EBSL37M
• Description: Embedded Processor 352-Pin BGA
• Manufacturer: Intel

Specifications of FW82371EBSL37M

• Package: 352BGA

Intel
15.
Problem:
Implication: The incorrect count causes the PIIX4/PIIX4E/PIIX4M to confuse sector boundaries, resulting in
Workaround: The work around for this erratum is to not perform Non-Data register reads while an IDE PIO
Status:
16.
Problem:
Implication: The errata condition can occur in Intel Pentium II processor/PIIX4x systems that use I/O Trap SMI
Workaround: The I/O Trap SMI with I/O Restart feature should be disabled if STPCLK# throttling is used. For
Status:
30
®
82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M
IDE Prefetch
While executing a PIO IDE Read Sector(s) or Read Multiple command with PIO pre-fetching
enabled, a read of a non-Data Register (such as ALT STATUS Register) may cause the
PIIX4/PIIX4E/PIIX4M PIO pre-fetch counter to increment, incorrectly since it should only
increment on data transfers.
invalid data being placed in memory. This erratum was observed during validation testing
executing special test software. No reports from internal testing or customer testing on production
systems (i.e., without special test software) have been attributed to this erratum to date. Intel
customers should perform their own risk analysis on this erratum and determine the most
appropriate work around for their systems.
transfer is taking place. In cases where this erratum has been seen, an interrupt (IRQn or SMI) has
been used to enter the code from which the ALT STATUS read occurs. Code which is not directly
involved in the IDE transfer should not perform the ALT STATUS read to check status of IDE
transfers. An alternative for PIIX4x-based systems is to use IDE device idle timer to detect IDE
activity. Another work around is to disable IDE PIO prefetching.
This will not be fixed in the PIIX4/PIIX4E/PIIX4M. This is planned to be incorporated into the
PIIX4 datasheet as a specification change. An additional paper titled “82371FB PIIX, 82371SB
PIIX3, 82371AB PIIX4, 82371EB PIIX4E IDE Prefetch Errata Description” is available from
Intel, that describes this erratum and risk analysis in greater detail. Intel is releasing this
information to various operating systems, BIOS vendors, and other software developers to allow
them to analyze their code base and to minimize the potential for future software programs to
trigger this erratum.
SMI# Timing
When the PIIX4/PIIX4E/PIIX4M assert STPCLK# at the same time that it traps an I/O cycle, the
SMI# assertion may be delayed until 5 PCI clocks after STPCLK# is deasserted. If this occurs, the
Intel
and subsequent instructions will be executed prior to the intended SMI code execution. If the I/O
restart feature of the processor is used, this could cause the processor to restart the wrong
instruction, resulting in undefined processor behavior. Software in which the instruction that follow
the trapped I/O instruction is dependent on a result returned by the I/O Trap SMI routine, may not
execute correctly. PIIX4/PIIX4E/PIIX4M I/O trap SMI includes device traps and APM register
write traps (0B2h).
with STPCLK# throttling enabled. The observed effect of the erratum is a system hang, although it
may also result in indeterminate code behavior that could cause data corruption.
applications where the I/O restart is not used, a dummy I/O instruction should follow the trapped
I/O instruction to ensure that the I/O trap SMI handler will be called before the result of that
handler is required. The system designer should review any I/O Trap SMI implementations for
impact based on their specific code execution sequence.
There are currently no plans to fix this erratum.
®
Pentium
®
II processor will not recognize the SMI on the intended I/O instruction boundary
Specification Update
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