FW82371EBSL37M Intel, FW82371EBSL37M Datasheet - Page 35

• Manufacturer Part Number: FW82371EBSL37M
• Description: Embedded Processor 352-Pin BGA
• Manufacturer: Intel

Specifications of FW82371EBSL37M

• Package: 352BGA

Specification Clarifications
1.
2.
Specification Update
R
CONFIG[1] Definition
Section 2.1.12, Other System and Test Signals, of the PIIX4 datasheet defines the CONFIG [1]
signal. In addition to controlling the polarity of INIT and CPURST, this signal also controls the
latching of NMI, SMI#, INTR, and INIT. In an Intel Pentium Processor-based system
(CONFIG[1]=0) NMI, SMI#, INTR, and INIT flow unlatched to the processor in all power
managed states. In a Pentium Pro Processor based system (CONFIG[1]=1) NMI, SMI#, INTR,
and INIT will be latched when STPCLK# is asserted, and held for 5 PCICLKs after STPCLK# is
deasserted.
This clarification applies to all steppings of the PIIX4/PIIX4E/PIIX4M and is planned to be
incorporated into the next revision of the PIIX4 datasheet.
2.1.12 Other System and Test Signals
SUSA#, SUSB# and SUSC# State Transition during RESET
After a hard reset (a write to CF9h bit 2, with bit 1 set to 1) SUSA#, SUSB#, SUSC# immediately
transitions low for three to four RTC clocks.
In many system designs, these signals control the various power planes. If the assertion of these
signals does not affect the state of PWROK from the power supply circuitry, the hard reset
completes normally with a system reboot. If the assertion of these signals causes the power supply
circuitry to deassert PWROK, the PIIX4/PIIX4E/PIIX4M will reset and power-up the system like
it was performing a cold boot. In both cases the system reboots.
This clarification applies to all steppings of the PIIX4/PIIX4E/PIIX4M and is planned to be
incorporated into the next revision of the PIIX4 datasheet.
CONFIG[1]
Name
Type
I
CONFIGURATION SELECT 1: This input signal is used to select the
type of microprocessor is being used in the system. If CONFIG[1] = 0,
the system contains an Intel
the system contains an Intel
used to control the polarity of the INIT and CPURST signals and the
latching of NMI, SMI#, INTR, and INIT. If CONFIG[1]=1, INIT# and
CPURST# are active low and NMI, SMI#, INTR, INIT# flow unlatched
to the processor. If CONFIG[1]=0, INIT and CPURST and active high
and NMI, SMI#, INTR, and INIT will be latched when STPCLK# is
asserted, and held for 5 PCICLKs after STPCLK# is deasserted.
Intel
®
82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M
®
®
Description
Pentium
Pentium
®
®
processor. If CONFIG[1] = 1,
Pro processor. CONFIG[1] is
35