FW82371EBSL37M Intel, FW82371EBSL37M Datasheet - Page 43

• Manufacturer Part Number: FW82371EBSL37M
• Description: Embedded Processor 352-Pin BGA
• Manufacturer: Intel

Specifications of FW82371EBSL37M

• Package: 352BGA

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Specification Update
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No Disabling Burst Events during a Burst
Burst events cause the reload of a Burst timer, which begins to count down from its loaded value.
While the timer is counting, the system returns to full clock operation. Once the burst timer
expires, the system automatically returns to the clock controlled state. PIIX4 provides two different
burst timers, a fast burst timer (which generates a short count) and a slow burst timer (which
generates a longer count). If burst events are disabled during a burst, the PIIX4 will enter the
clock-controlled state after the burst timer expires and will not be able to break out.
This clarification applies to all steppings of the PIIX4/PIIX4E/PIIX4M and is planned to be
incorporated into the next revision of the PIIX4 datasheet.
Unrouting a PIRQ
Section 8.6.8, Interrupt Steering, of the PIIX4 datasheet, states how to route a PIRQx# to a IRQx,
but does not state a suggested procedure for unrouting. The paragraph below will be added at the
end of this section.
Before unrouting a PIRQx# from an IRQx, ensure that the mask is enabled for that IRQ and that
the corresponding ELCR is set back to edge mode. When the IRQx is unmasked an interrupt will
likely be generated which should be treated as any other spurious interrupt.
This clarification applies to all steppings of the PIIX4/PIIX4E/PIIX4M and is planned to be
incorporated into the next revision of the PIIX4 datasheet.
IDE Device Detection
Values read from an unpopulated, floating IDE port are indeterminate. To avoid falsely detecting a
busy drive, OEMs should follow the platform design recommendations for detecting an IDE
device.
This clarification applies to all steppings of the PIIX4/PIIX4E/PIIX4M and is planned to be
incorporated into the next revision of the PIIX4 datasheet.
Physical Region Descriptor Alignment
In the PIIX4 datasheet, Section 9.4, Bus Master Function, the Physical Region Descriptor Format
inaccurately specifies that the Descriptor Table (DT) must be aligned on a 64-Kbyte boundary.
The Physical Region Descriptor Table must be aligned on a DWord boundary. However, the DT
must never cross a 64-Kbyte boundary. For the case where a 64-Kbyte DT is required, then it must
be aligned on a 64-Kbyte boundary.
This clarification applies to all steppings of the PIIX4/PIIX4E/PIIX4M and is planned to be
incorporated into the next revision of the PIIX4 datasheet.
Intel
®
82371AB PIIX4, 82371EB PIIX4E, 82371MB PIIX4M
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