PIC18F4585-H/P Microchip Technology, PIC18F4585-H/P Datasheet - Page 190

• Manufacturer Part Number: PIC18F4585-H/P
• Description: IC MCU 8BIT 48KB FLASH 40PDIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4585-H/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2585/2680/4585/4680
17.3.1
The MSSP module has four registers for SPI mode
operation. These are:
• MSSP Control Register 1 (SSPCON1)
• MSSP Status Register (SSPSTAT)
• Serial Receive/Transmit Buffer Register
• MSSP Shift Register (SSPSR) – Not directly
SSPCON1 and SSPSTAT are the control and status
registers in SPI mode operation. The SSPCON1
register is readable and writable. The lower 6 bits of
the SSPSTAT are read-only. The upper two bits of the
SSPSTAT are read/write.
REGISTER 17-1:
DS39625C-page 188
(SSPBUF)
accessible
REGISTERS
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSPSTAT: MSSP STATUS REGISTER (SPI MODE)
bit 7
SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
CKE: SPI Clock Select bit
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
Polarity of clock state is set by the CKP bit (SSPCON1<4>).
D/A: Data/Address bit
Used in I
P: Stop bit
Used in I
cleared.
S: Start bit
Used in I
R/W: Read/Write bit Information
Used in I
UA: Update Address bit
Used in I
BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Legend:
R = Readable bit
-n = Value at POR
R/W-0
SMP
2
2
2
2
2
C mode only.
C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is
C mode only.
C mode only.
C mode only.
R/W-0
CKE
W = Writable bit
‘1’ = Bit is set
D/A
Preliminary
R-0
R-0
SSPSR is the shift register used for shifting data in or
out. SSPBUF is the buffer register to which data bytes
are written to or read from.
In receive operations, SSPSR and SSPBUF together
create a double-buffered receiver. When SSPSR
receives a complete byte, it is transferred to SSPBUF
and the SSPIF interrupt is set.
During transmission, the SSPBUF is not double-
buffered. A write to SSPBUF will write to both SSPBUF
and SSPSR.
P
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R-0
S
R/W
R-0
© 2007 Microchip Technology Inc.
x = Bit is unknown
R-0
UA
R-0
BF
bit 0