PXAH30KFBE,557 NXP Semiconductors, PXAH30KFBE,557 Datasheet - Page 25
PXAH30KFBE,557
Manufacturer Part Number
PXAH30KFBE,557
Description
IC XA MCU 16BIT CMOS 100LQFP
Manufacturer
NXP Semiconductors
Series
XAr
Datasheet
1.PXAH30KFBE.pdf
(36 pages)
Specifications of PXAH30KFBE,557
Core Processor
XA
Core Size
16-Bit
Speed
30MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
DMA, WDT
Number Of I /o
33
Program Memory Size
-
Program Memory Type
ROMless
Eeprom Size
-
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
-
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PXAH30KFBE,557
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
Table 7. UART0 Interrupts (Interrupt structure is the same except for bit locations for all 4 UARTs)
EXCEPTION/TRAPS PRECEDENCE
1999 Sep 24
Rx Character Available
CRC/Framing Error
Rx Overrun
Parity Error
Tx Buffer Empty
Break/Abort
Tx Underrun/EOM
CTS
DCD
Zero Count
Reset (h/w, watchdog, s/w)
Break Point
Trace
Stack Overflow
Divide by 0
User RETI
TRAP 0–15 (software)
CMOS 16-bit highly integrated microcontroller
Potential
Interrupt
UART0
Description
–
–
–
See WR1[1]
Individual Enable Bit
WR1[2]
802[2]
Break/
Abort IE
WR15[7]
81E[7]
Tx Underrun/EOM IE
WR15[6]
81E[6]
CTS IE
WR15[5]
81E[5]
DCD IE
WR15[3]
81E[3]
Zero Count IE
WR15[1]
81E[1]
MMR Hex Offset
MMR Hex Offset
RR0[0]
820[0]
RR1[6]
822[6]
RR1[5]
822[5]
RR1[4]
822[4]
RR0[2]
820[2]
RR0[7]
820[7]
RR0[6]
820[6]
RR0[5]
820[5]
RR0[3]
820[3]
RR0[1]
820[1]
Source Bit
Vector Address
000C–000F
0008–000B
0000–0003
0004–0007
0010–0013
0014–0017
0040–007F
25
WR1[4:3]
802[4:3]
Tx Interrupt Enable
WR1[1]
802[1]
Master External/Status
Interrupt Enable
WR1[0]
802[0]
Group Enable Bit(S)
MMR Hex Offset
Even Channel Rx IP
RR3[5]
826[5]
Even Channel Tx IP
RR3[4]
826[4]
Even Channel
External/Status IP
RR3[3]
826[3]
MMR Hex Offset
Group Flag Bit
Arbitration Ranking
0 (High)
1
1
1
1
1
1
Preliminary specification
Master Enable Bit
UART0/1 Master
Interrupt Enable
WR9[3]
812[3]
MMR Hex Offset
XA-H3