B300D44A102XXG ON Semiconductor, B300D44A102XXG Datasheet - Page 15

• Manufacturer Part Number: B300D44A102XXG
• Description: IC PROCESSOR AUDIO 24BIT 44DFN
• Manufacturer: ON Semiconductor
• Series: BelaSigna® 300r
• Type: Audio Processorr

Specifications of B300D44A102XXG

• Applications: Portable Equipment
• Mounting Type: Surface Mount
• Package / Case: 44-VFDFN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: B300D44A102XXG; B300D44A102XXGOSTR

HEAR Configurable Accelerator
optimized signal processing engine that is configured
through the CFX. It offers high speed, high flexibility and
high
consumption. For added computing precision, the HEAR
supports block floating point processing. Configuration of
the HEAR is performed using the HEAR configuration tool
(HCT). For further information on the usage of the HEAR
and the HCT, please refer to the HEAR Configurable
Accelerator Reference Manual.
including but not limited to the following:
efficiently, the HEAR excels at the following:
Table 12. CFX SUMMARY INSTRUCTION SET
The HEAR Configurable Accelerator is a highly
The HEAR is optimized for advanced audio algorithms,
To provide the ability for these algorithms to be executed
SUBMULADD
SUBMULNEG
SUBMULSUB
♦
♦
♦
♦
♦
♦
♦
♦
Instruction
SUBSTEP
RETURNI
SUBMUL
STORE
SUBSH
filterbank or FFT
SLEEP
Dynamic range compression
Directional processing
Acoustic echo cancellation
Noise reduction
Processing using a weighted overlap add (WOLA)
Time domain filtering
Subband filtering
Attack/release filtering
SWAP
SHRA
SHRL
SHLL
SUB
XOR
performance,
Return from an interrupt
Shift a data register left logically
Shift a data register right arithmetically
Shift a data register right logically
Enter sleep mode and wait for an interrupt and then wake up from sleep mode
Store data, a register or accumulator in a register, accumulator or memory location
Subtract two data registers or accumulators, storing the result in a data register or accumulator
Subtract two XY data registers, multiply the result by a third XY data register, and store the result in an accumulator
Subtract two XY data registers, multiply the result by a third XY data register, and add the result to an accumulator
Subtract two XY data registers, multiply the result by a third XY data register, negate the result and store it in an
accumulator
Subtract two XY data registers, multiply the result by a third XY data register, and subtract the result from an accu-
mulator
Subtract two data registers or two accumulators and shift right one bit, storing the result in a data register or accu-
mulator
Subtract a step register from the corresponding pointer
Swap the contents of two data registers, conditionally
Perform a bitwise XOR operation on two data registers or a data register and a value, storing the result in a data
register
while
maintaining
low
(continued)
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power
15
Input/Output Controller (IOC)
all audio samples transferred in the system. The IOC can
manage any system configuration and route the data
accordingly. It is an advanced audio DMA unit.
Memory
RAM & ROM
structures are shown in Table 13:
Description
Table 13. RAM AND ROM STRUCTURE
Program memory (ROM)
Program memory (RAM)
X memory (RAM)
Math library LUT (ROM)
Y memory (RAM)
The IOC is responsible for the automated data moves of
The size and width of each of the RAM and ROM
♦
♦
Memory Structure
correlation)
Vector addition/subtraction/multiplication
Signal statistics (such as average, variance and
Data Width
32
32
24
24
24
Memory Size
12288
2048
6144
2048
128