B300D44A102XXG ON Semiconductor, B300D44A102XXG Datasheet - Page 9

• Manufacturer Part Number: B300D44A102XXG
• Description: IC PROCESSOR AUDIO 24BIT 44DFN
• Manufacturer: ON Semiconductor
• Series: BelaSigna® 300r
• Type: Audio Processorr

Specifications of B300D44A102XXG

• Applications: Portable Equipment
• Mounting Type: Surface Mount
• Package / Case: 44-VFDFN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: B300D44A102XXG; B300D44A102XXGOSTR

DFN Assembly / Design Notes
metal slug under the package. If the design has traces under
or routing under the PCB, the solder mask should not be so
thick that it impedes a good electrical connection on both
sides of the DFN. Exposed vias under the DFN are not
recommended.
yield with the fine pitch on the DFN pads.
application note:
http://www.onsemi.com/pub/Collateral/AND8211−D.PDF
Recommended Circuit Design Guidelines
processing in a single system. Due to the mixed−signal
Table 8. DFN PAD DESCRIPTIONS
There is no requirement for electrical connection to the
A 0.004″ solder paste stencil has shown good assembly
More detailed assembly guidelines can be found in this
BelaSigna 300 is designed to allow both digital and analog
Pad Index
28
32
31
30
29
37
36
35
27
26
25
24
23
VDDO_SPI
SPI_CLK
SPI_SERI
SPI_CS
SPI_SERO
SDA (I2C)
SCL (I2C)
EXT_CLK
PCM_FR
PCM_SERI
PCM_SERO
PCM_CLK
Reserved
BelaSigna 300 Pad Name
(continued)
Figure 1. Schematic of Ground Scheme
Supply for SPI interface I/O
Serial peripheral interface clock
Serial peripheral interface input
Serial peripheral interface chip select
Serial peripheral interface output
I2C data
I2C clock
External clock input/internal clock output
PCM interface frame
PCM interface input
PCM interface output
PCM interface clock
Reserved
http://onsemi.com
9
nature of this system, the careful design of the printed circuit
board (PCB) layout is critical to maintain the high audio
fidelity of BelaSigna 300. To avoid coupling noise into the
audio signal path, keep the digital traces away from the
analog traces. To avoid electrical feedback coupling, isolate
the input traces from the output traces.
Recommended Ground Design Strategy
analog ground plane (AGND) and the digital ground plane
(DGND). These two planes should be connected together at
a single point, known as the star point. The star point should
be located at the ground terminal of a capacitor on the output
of the power regulator as illustrated in Figure 1.
The ground plane should be partitioned into two: the
Description
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
A/D
A
D
D
D
D
D
D
D
D
D
D
D