B300D44A102XXG ON Semiconductor, B300D44A102XXG Datasheet - Page 23

• Manufacturer Part Number: B300D44A102XXG
• Description: IC PROCESSOR AUDIO 24BIT 44DFN
• Manufacturer: ON Semiconductor
• Series: BelaSigna® 300r
• Type: Audio Processorr

Specifications of B300D44A102XXG

• Applications: Portable Equipment
• Mounting Type: Surface Mount
• Package / Case: 44-VFDFN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: B300D44A102XXG; B300D44A102XXGOSTR

Internal Band Gap Reference Voltage
temperature and process variations. This reference voltage
is used in the generation of all of the regulated voltages in the
BelaSigna 300 system and provides a nominal 1 V reference
signal to all components using the reference voltage.
Internal Digital Supply Voltage (VDDC)
voltage for all internal digital components, including being
used as the interface voltage at the low side of the level
translation circuitry attached to all of the external digital
pads. VDDC is also provided as an output pad, where a
capacitor to ground typically filters power supply noise. The
VDDC internal regulator is a programmable power supply
that allows the selection of the lowest digital supply
depending on the clock frequency at which BelaSigna 300
will operate. In the WLCSP package, the VDDC
configuration is set by the boot ROM to its maximum value
to allow for 40 MHz operation in all parts. In the DFN
package, VDDC is not set by the boot ROM. Thus, care must
be taken when using the DFN at high clock frequencies to
ensure that the VDDC configuration is properly set. Contact
ON Semiconductor for more information regarding VDDC
calibration.
External Digital Supply Voltage (VDDO)
by the pads of BelaSigna 300. Communication with external
devices will happen at the level defined on this pin. This pin
is not available on the WLCSP option of BelaSigna 300, as
it is internally connected to VBAT.
SPI Port Digital Supply Voltage (VDDO_SPI)
dedicated to the SPI port. Communication with external
EEPROMs will happen at the level defined on this pin. This
pin is not available on the WLCSP option of BelaSigna 300,
as it is internally connected to VBAT.
Regulated Supply Voltage (VREG)
available externally to allow for additional noise filtering of
the regulated voltages within the system.
Regulated Doubled Supply Voltage (VDBL)
internal charge pump. It is a reference to the analog circuitry.
It is available externally to allow for additional noise
filtering of the regulated voltages within the system.
is periodically refreshed to maintain the 2 V supply. The
charge pump refresh frequency is derived from slow clock
which assists the input stage in filtering out any noise
generated by the dynamic current draw on this supply
voltage.
The band gap reference voltage has been stabilized over
The internal digital supply voltage is used as the supply
VDDO is an externally provided power source. It is used
VDDO_SPI is an externally provided power source
VREG is a 1 V reference to the analog circuitry. It is
VDBL is a 2 V reference voltage generated from the
The internal charge pump uses an external capacitor that
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23
Voltage Mode
supply mode. This mode allows integration into a wide
variety of devices with a range of voltage supplies and
communications levels. BelaSigna 300 operates from a
nominal supply of 1.8 V on VBAT, but this can scale
depending on available supply. The digital logic runs on an
internally generated regulated voltage (VDDC), in the range
of 0.9 V to 1.2 V. On the WLCSP package option, all digital
I/O pads including the SPI port run from the same voltage as
supplied on VBAT. On the DFN package option, the VDDO
and VDDO_SPI power sources determine these voltage levels.
power−on−reset (POR) functionality as well as power
supervisory circuitry. These two components work together
to ensure proper device operation under all battery conditions.
supply voltage (VBAT) and the internal digital supply
voltage (VDDC). This circuit is used to start the system
when VBAT reaches a safe startup voltage, and to reset the
system when either of the VBAT or VDDC voltages drops
below a relevant voltage threshold. The relevant threshold
voltages are shown in Table 15.
Power−on−Reset (POR) and Booting Sequence
system behavior during start−up and proper system
configuration after start−up. At the start of the POR
sequence, the audio output is disabled and all configuration
and control registers are asynchronously reset to their
default values (as specified in the Hardware Reference
Manual for BelaSigna 300). All CFX DSP registers are
cleared and the contents of all RAM instances are
unspecified at this point.
stabilization and boot ROM initialization. During the
voltage supply stabilization phase, the following steps are
performed:
Table 15. POWER MANAGEMENT THRESHOLDS
VBAT monitor startup
VBAT startup
VBAT and VDDC shutdown
BelaSigna 300 operates in: Low voltage (LV) power
The power management on BelaSigna 300 includes the
The power supervisory circuitry monitors both the battery
BelaSigna 300 uses a POR sequence to ensure proper
The POR sequence consists of two phases: voltage supply
1. The internal regulators are enabled and allowed to
2. The internal charge pump is enabled and allowed
3. SYSCLK is connected to all of the system
4. The system switches to external clocking mode
stabilize.
to stabilize.
components.
(WLCSP package option only)
Threshold
0.70 V
0.82 V ± 50 mV
0.80 V ± 50 mV
Voltage Level