C8051F700-GQR Silicon Laboratories Inc, C8051F700-GQR Datasheet - Page 119

no-image

C8051F700-GQR

Manufacturer Part Number
C8051F700-GQR
Description
MCU 8-Bit C8051F70x 8051 CISC 15KB Flash 1.8V/3V 64-Pin TQFP T/R
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of C8051F700-GQR

Package
64TQFP
Device Core
8051
Family Name
C8051F70x
Maximum Speed
25 MHz
Ram Size
512 Byte
Program Memory Size
15 KB
Operating Supply Voltage
1.8|3 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
54
Interface Type
I2C/SMBus/SPI/UART
On-chip Adc
16-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
4

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F700-GQR
Manufacturer:
APTINA
Quantity:
1 001
Part Number:
C8051F700-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
SFR Definition 18.3. EMI0TC: External Memory Timing Control
SFR Address = 0xEE; SFR Page = F
Name
Reset
Bit
7:6
5:2
1:0
Type
Bit
EWR[3:0]
EAH[1:0]
EAS[1:0]
Name
7
1
EAS[1:0]
R/W
EMIF Address Setup Time Bits.
00: Address setup time = 0 SYSCLK cycles.
01: Address setup time = 1 SYSCLK cycle.
10: Address setup time = 2 SYSCLK cycles.
11: Address setup time = 3 SYSCLK cycles.
EMIF WR and RD Pulse-Width Control Bits.
0000: WR and RD pulse width = 1 SYSCLK cycle.
0001: WR and RD pulse width = 2 SYSCLK cycles.
0010: WR and RD pulse width = 3 SYSCLK cycles.
0011: WR and RD pulse width = 4 SYSCLK cycles.
0100: WR and RD pulse width = 5 SYSCLK cycles.
0101: WR and RD pulse width = 6 SYSCLK cycles.
0110: WR and RD pulse width = 7 SYSCLK cycles.
0111: WR and RD pulse width = 8 SYSCLK cycles.
1000: WR and RD pulse width = 9 SYSCLK cycles.
1001: WR and RD pulse width = 10 SYSCLK cycles.
1010: WR and RD pulse width = 11 SYSCLK cycles.
1011: WR and RD pulse width = 12 SYSCLK cycles.
1100: WR and RD pulse width = 13 SYSCLK cycles.
1101: WR and RD pulse width = 14 SYSCLK cycles.
1110: WR and RD pulse width = 15 SYSCLK cycles.
1111: WR and RD pulse width = 16 SYSCLK cycles.
EMIF Address Hold Time Bits.
00: Address hold time = 0 SYSCLK cycles.
01: Address hold time = 1 SYSCLK cycle.
10: Address hold time = 2 SYSCLK cycles.
11: Address hold time = 3 SYSCLK cycles.
6
1
5
1
Rev. 1.0
4
1
EWR[3:0]
R/W
Function
3
1
C8051F70x/71x
2
1
1
1
EAH[1:0]
R/W
0
1
119

Related parts for C8051F700-GQR