C8051F700-GQR Silicon Laboratories Inc, C8051F700-GQR Datasheet - Page 238

• Manufacturer Part Number: C8051F700-GQR
• Description: MCU 8-Bit C8051F70x 8051 CISC 15KB Flash 1.8V/3V 64-Pin TQFP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F700-GQR

• Package: 64TQFP
• Device Core: 8051
• Family Name: C8051F70x
• Maximum Speed: 25 MHz
• Ram Size: 512 Byte
• Program Memory Size: 15 KB
• Operating Supply Voltage: 1.8|3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 54
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 16-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4

C8051F70x/71x
238
Table 30.5. SMBus Status Decoding: Hardware ACK Disabled (EHACK = 0) (Continued)
0010 0
0001 0
0000 1
1100
1110
Values Read
Values Read
Table 30.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1)
0
0
0
1 X
1 X
1 X
0 X
0
0
0
1
Lost arbitration while attempt-
ing a repeated START.
Lost arbitration due to a
detected STOP.
Lost arbitration while transmit-
ting a data byte as master.
A master START was gener-
ated.
A master data or address byte
was transmitted; NACK
received.
A master data or address byte
was transmitted; ACK
received.
Current SMbus State
Current SMbus State
Rev. 1.0
Abort failed transfer.
Reschedule failed transfer.
Abort failed transfer.
Reschedule failed transfer.
Abort failed transfer.
Reschedule failed transfer.
Load slave address + R/W into
SMB0DAT.
Set STA to restart transfer.
Abort transfer.
Load next data byte into
SMB0DAT.
End transfer with STOP.
End transfer with STOP and start
another transfer.
Send repeated START.
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT). Set ACK for initial
data byte.
Typical Response Options
Typical Response Options
Values to
Values to
0
1
0
1
0
1
0
1
0
0
0
1
1
0
Write
Write
0 X
0 X
0 X
0 X
0 0
0 0
0 X 1100
0 X
1 X
0 X 1100
1 X
1 X
0 X
0 1
1000
1110
1110
1110
1110
1110
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