C8051F700-GQR Silicon Laboratories Inc, C8051F700-GQR Datasheet - Page 166

• Manufacturer Part Number: C8051F700-GQR
• Description: MCU 8-Bit C8051F70x 8051 CISC 15KB Flash 1.8V/3V 64-Pin TQFP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F700-GQR

• Package: 64TQFP
• Device Core: 8051
• Family Name: C8051F70x
• Maximum Speed: 25 MHz
• Ram Size: 512 Byte
• Program Memory Size: 15 KB
• Operating Supply Voltage: 1.8|3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 54
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 16-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4

C8051F70x/71x
SFR Definition 25.1. VDM0CN: V
SFR Address = 0xFF; SFR Page = All Pages
25.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Section “9. Electrical Characteristics”
on page 47 for complete RST pin specifications. The PINRSF flag (RSTSRC.0) is set on exit from an exter-
nal reset.
25.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than the MCD timeout, the one-shot will time out and generate a reset.
After a MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; oth-
erwise, this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 dis-
ables it. The state of the RST pin is unaffected by this reset.
166
Name
Reset
5:0
Bit
Type
7
6
Bit
VDDSTAT
VDMEN
Unused
VDMEN
Name
Varies
R/W
7
VDDSTAT
V
This bit turns the V
tem resets until it is also selected as a reset source in register RSTSRC (SFR Def-
inition 25.2). Selecting the V
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the V
reset source.
0: V
1: V
V
This bit indicates the current power supply status (V
0: V
1: V
Read = Varies; Write = Don’t care.
Varies
DD
DD
R
6
DD
DD
DD
DD
Monitor Enable.
Status.
Monitor Disabled.
Monitor Enabled.
is at or below the V
is above the V
Varies
R
5
DD
DD
DD
monitor circuit on/off. The V
Monitor Control
monitor threshold.
Varies
Rev. 1.0
DD
R
4
DD
monitor threshold.
monitor as a reset source before it has stabilized
Function
Varies
R
3
Varies
DD
R
2
DD
DD
Monitor cannot generate sys-
Monitor and selecting it as a
Monitor output).
Varies
R
1
Varies
R
0