C8051F700-GQR Silicon Laboratories Inc, C8051F700-GQR Datasheet - Page 142

• Manufacturer Part Number: C8051F700-GQR
• Description: MCU 8-Bit C8051F70x 8051 CISC 15KB Flash 1.8V/3V 64-Pin TQFP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F700-GQR

• Package: 64TQFP
• Device Core: 8051
• Family Name: C8051F70x
• Maximum Speed: 25 MHz
• Ram Size: 512 Byte
• Program Memory Size: 15 KB
• Operating Supply Voltage: 1.8|3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 54
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 16-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4

C8051F70x/71x
SFR Definition 21.3. EIE1: Extended Interrupt Enable 1
SFR Address = 0xE6; SFR Page = All Pages
142
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
Reserved Must write 0.
EWADC0 Enable Window Comparison ADC0 interrupt.
EADC0
ESMB0
EPCA0
Name
EMAT
ECP0
ET3
R/W
ET3
7
0
Enable Timer 3 Interrupt.
This bit sets the masking of the Timer 3 interrupt.
0: Disable Timer 3 interrupt.
1: Enable interrupt requests generated by the TF3L or TF3H flags.
Enable Comparator0 (CP0) Interrupt.
This bit sets the masking of the CP0 rising edge or falling edge interrupt.
0: Disable CP0 interrupts.
1: Enable interrupt requests generated by the CP0RIF and CP0FIF flags.
Enable Programmable Counter Array (PCA0) Interrupt.
This bit sets the masking of the PCA0 interrupts.
0: Disable all PCA0 interrupts.
1: Enable interrupt requests generated by PCA0.
Enable ADC0 Conversion Complete Interrupt.
This bit sets the masking of the ADC0 Conversion Complete interrupt.
0: Disable ADC0 Conversion Complete interrupt.
1: Enable interrupt requests generated by the AD0INT flag.
This bit sets the masking of ADC0 Window Comparison interrupt.
0: Disable ADC0 Window Comparison interrupt.
1: Enable interrupt requests generated by ADC0 Window Compare flag (AD0WINT).
Enable Port Match Interrupts.
This bit sets the masking of the Port Match event interrupt.
0: Disable all Port Match interrupts.
1: Enable interrupt requests generated by a Port Match.
Enable SMBus (SMB0) Interrupt.
This bit sets the masking of the SMB0 interrupt.
0: Disable all SMB0 interrupts.
1: Enable interrupt requests generated by SMB0.
Reserved
R/W
6
0
ECP0
R/W
5
0
EPCA0
R/W
Rev. 1.0
4
0
Function
EADC0
R/W
3
0
EWADC0
R/W
2
0
EMAT
R/W
1
0
ESMB0
R/W
0
0