C8051F700-GQR Silicon Laboratories Inc, C8051F700-GQR Datasheet - Page 213

• Manufacturer Part Number: C8051F700-GQR
• Description: MCU 8-Bit C8051F70x 8051 CISC 15KB Flash 1.8V/3V 64-Pin TQFP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F700-GQR

• Package: 64TQFP
• Device Core: 8051
• Family Name: C8051F70x
• Maximum Speed: 25 MHz
• Ram Size: 512 Byte
• Program Memory Size: 15 KB
• Operating Supply Voltage: 1.8|3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 54
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 16-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4

29.2. 32-bit CRC Algorithm
The C8051F70x/71x CRC unit calculates the 32-bit CRC using a poly of 0x04C11DB7. The CRC-32 algo-
rithm is "reflected", meaning that all of the input bytes and the final 32-bit output are bit-reversed in the pro-
cessing engine. The following is a description of a simplified CRC algorithm that produces results identical
to the hardware:
1. XOR the least-significant byte of the current CRC result with the input byte. If this is the first iteration of
2. Right-shift the CRC result.
3. If the LSB of the CRC result is set, XOR the CRC result with the reflected polynomial (0xEDB88320).
4. Repeat at Step 2 for the number of input bits (8).
For example, the 32-bit C8051F70x/71x CRC algorithm can be described by the following code:
unsigned long UpdateCRC (unsigned long CRC_acc, unsigned char CRC_input){
}
Table 29.2 lists example input values and the associated outputs using the 32-bit C8051F70x/71x CRC
algorithm (an initial value of 0xFFFFFFFF is used):
the CRC unit, the current CRC result will be the set initial value (0x00000000 or 0xFFFFFFFF).
unsigned char i; // loop counter
#define POLY 0xEDB88320 // bit-reversed version of the poly 0x04C11DB7
// Create the CRC "dividend" for polynomial arithmetic (binary arithmetic
// with no carries)
CRC_acc = CRC_acc ^ CRC_input;
// "Divide" the poly into the dividend using CRC XOR subtraction
// CRC_acc holds the "remainder" of each divide
// Only complete this division for 8 bits since input is 1 byte
for (i = 0; i < 8; i++)
{
}
return CRC_acc; // Return the final remainder (CRC value)
// Check if the MSB is set (if MSB is 1, then the POLY can "divide"
// into the "dividend")
if ((CRC_acc & 0x00000001) == 0x00000001)
{
}
else
{
}
// if so, shift the CRC value, and XOR "subtract" the poly
CRC_acc = CRC_acc >> 1;
CRC_acc ^= POLY;
// if not, just shift the CRC value
CRC_acc = CRC_acc >> 1;
0x00, 0x00, 0xAA, 0xBB, 0xCC
0xAA, 0xBB, 0xCC
Table 29.2. Example 32-bit CRC Outputs
Input
0x63
Rev. 1.0
0x78D129BC
0x41B207B3
0xF9462090
Output
C8051F70x/71x
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