C8051F700-GQR Silicon Laboratories Inc, C8051F700-GQR Datasheet - Page 239

• Manufacturer Part Number: C8051F700-GQR
• Description: MCU 8-Bit C8051F70x 8051 CISC 15KB Flash 1.8V/3V 64-Pin TQFP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F700-GQR

• Package: 64TQFP
• Device Core: 8051
• Family Name: C8051F70x
• Maximum Speed: 25 MHz
• Ram Size: 512 Byte
• Program Memory Size: 15 KB
• Operating Supply Voltage: 1.8|3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 54
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 16-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4

Table 30.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1) (Continued)
1000
0100
0101 0 X X
Values Read
0
0
0
0
0
0
0
0
0
1 X
1
0
0
1
A master data byte was
received; ACK sent.
A master data byte was
received; NACK sent (last
byte).
A slave byte was transmitted;
NACK received.
A slave byte was transmitted;
ACK received.
A Slave byte was transmitted;
error detected.
An illegal STOP or bus error
was detected while a Slave
Transmission was in progress.
Current SMbus State
Rev. 1.0
Set ACK for next data byte;
Read SMB0DAT.
Set NACK to indicate next data
byte as the last data byte;
Read SMB0DAT.
Initiate repeated START.
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
Read SMB0DAT; send STOP.
Read SMB0DAT; Send STOP
followed by START.
Initiate repeated START.
Switch to Master Transmitter
Mode (write to SMB0DAT before
clearing SI).
No action required (expecting
STOP condition).
Load SMB0DAT with next data
byte to transmit.
No action required (expecting
Master to end transfer).
Clear STO.
Typical Response Options
C8051F70x/71x
Values to
0
0
0
1
0
1
1
0
0
0
0
0
Write
0 1
0 0
0 0
0 X 1100
1 0
1 0
0 0
0 X 1100
0 X 0001
0 X 0100
0 X 0001
0 X
1000
1000
1110
1110
1110
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