LPC2420FBD208-S NXP Semiconductors, LPC2420FBD208-S Datasheet - Page 30
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LPC2420FBD208-S
Manufacturer Part Number
LPC2420FBD208-S
Description
MCU 16-Bit/32-Bit LPC2000 ARM7TDMI-S RISC ROMLess 3.3V 208-Pin LQFP Tray
Manufacturer
NXP Semiconductors
Datasheet
1.LPC2460FBD208551.pdf
(79 pages)
Specifications of LPC2420FBD208-S
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Ram Size
82 KB
Operating Supply Voltage
3.3 V
Data Bus Width
16|32 Bit
Program Memory Type
ROMLess
Number Of Programmable I/os
160
Interface Type
I2C/I2S/SPI/SSP/UART/USB
On-chip Adc
8-chx10-bit
On-chip Dac
1-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
4
NXP Semiconductors
LPC2420_60_5
Preliminary data sheet
7.8.1 Features
7.8 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the
GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate
registers allow setting or clearing any number of outputs simultaneously. The value of the
output register may be read back as well as the current state of the port pins.
LPC2420/2460 use accelerated GPIO functions:
Additionally, any pin on port 0 and port 2 (total of 64 pins) that is not configured as an
analog input/output can be programmed to generate an interrupt on a rising edge, a falling
edge, or both. The edge detection is asynchronous, so it may operate when clocks are not
present such as during Power-down mode. Each enabled interrupt can be used to wake
the chip up from Power-down mode.
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One AHB master for transferring data. This interface transfers data when a DMA
request goes active.
32-bit AHB master bus width.
Incrementing or non-incrementing addressing for source and destination.
Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the
peripheral.
Internal four-word FIFO per channel.
Supports 8-bit, 16-bit, and 32-bit wide transactions.
An interrupt to the processor can be generated on a DMA completion or when a DMA
error has occurred.
Interrupt masking. The DMA error and DMA terminal count interrupt requests can be
masked.
Raw interrupt status. The DMA error and DMA count raw interrupt status can be read
prior to masking.
GPIO registers are relocated to the ARM local bus so that the fastest possible I/O
timing can be achieved.
Mask registers allow treating sets of port bits as a group, leaving other bits
unchanged.
All GPIO registers are byte and half-word addressable.
Entire port value can be written in one instruction.
Bit level set and clear registers allow a single instruction to set or clear any number of
bits in one port.
Direction control of individual bits.
All I/O default to inputs after reset.
Backward compatibility with other earlier devices is maintained with legacy port 0 and
port 1 registers appearing at the original addresses on the APB.
Rev. 05 — 24 February 2010
Flashless 16-bit/32-bit microcontroller
LPC2420/2460
© NXP B.V. 2010. All rights reserved.
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