SI3019-F-GSR Silicon Laboratories Inc, SI3019-F-GSR Datasheet - Page 31
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SI3019-F-GSR
Manufacturer Part Number
SI3019-F-GSR
Description
IC VOICE DAA GCI/PCM/SPI 16SOIC
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI3019-F-GSR.pdf
(112 pages)
Specifications of SI3019-F-GSR
Function
Data Access Arrangement (DAA)
Interface
GCI, PCM, SPI
Number Of Circuits
1
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
8.5mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
16-SOIC (3.9mm Width)
Includes
Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Lead Free Status / RoHS Status
Supplier Unconfirmed, Lead free / RoHS Compliant
the requirements of TBR21.
There
non-standard
350 + (1000 || 210 nF) impedance selection in
Register 30 is the ANSI/EIA/TIA 464 compromise
impedance network for trunks. The last ac termination
selection, ACIM[3:0] = 1111, is designed to satisfy
minimum return loss requirements for every country that
requires a complex termination. By selecting this
setting, the system is ensured to meet minimum PTT
requirements.
For each of the sixteen ac termination settings, the
programmable digital hybrid can be used to further
reduce near-end echo. See "5.28. Transhybrid Balance"
on page 37 for details.
ACIM[3:0]
Table 17. AC Termination Settings for the
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
1100
1101
0111
1110
1111
are
Si3019 Line-Side Device
two
ac
600
900
270 + (750 || 150 nF) and
275 + (780 || 150 nF)
220 + (820 || 120 nF) and 220
+ (820 || 115 nF)
370 + (620 || 310 nF)
320 + (1050 || 230 nF)
370 + (820 || 110 nF)
275 + (780 || 115 nF)
120 + (820 || 110 nF)
350 + (1000 || 210 nF)
200 + (680 || 100 nF)
600 + 2.16 µF
900 + 1 µF
900 + 2.16 µF
600 + 1 µF
Global complex impedance
selections
termination
AC Termination
useful
requirements.
for
satisfying
The
Rev. 1.31
5.18. Ring Detection
The ring signal is resistively coupled from TIP and RING
to the RNG1 and RNG2 pins. The Si3050 supports
either full- or half-wave ring detection. With full-wave
ring detection, the designer can detect a polarity
reversal of the ring signal. See “5.25.Caller ID” on
page 34. The ring detection threshold is programmable
with the RT bit (Register 16, bit 0) and RT2 bit
(Register 17, bit 4). The ring detector output can be
monitored in three ways. The first method uses the
RGDT pin. The second method uses the register bits,
RDTP, RDTN, and RDT (Register 5). The final method
uses the DTX output.
The ring detector mode is controlled by the RFWE bit
(Register 18, bit 1). When the RFWE bit is 0 (default
mode), the ring detector operates in half-wave rectifier
mode. In this mode, only positive ring signals are
detected. A positive ring signal is defined as a voltage
greater than the ring threshold across RNG1-RNG2.
Conversely, a negative ring signal is defined as a
voltage less than the negative ring threshold across
RNG1-RNG2. When the RFWE bit is 1, the ring detector
operates in full-wave rectifier mode. In this mode, both
positive and negative ring signals are detected.
The first method to monitor ring detection output uses
the RGDT pin. When the RGDT pin is used, it defaults
to active low, but can be changed to active high by
setting the RPOL bit (Register 14, bit 1). This pin is an
open-drain output, and requires a 4.7 k pullup or
pulldown for correct operation. If multiple RGDT pins
are connected to a single input, the combined pullup or
pulldown resistance should equal 4.7 k
When the RFWE bit is 0, the RGDT pin is asserted
when the ring signal is positive, which results in an
output signal frequency equal to the actual ring
frequency. When the RFWE bit is 1, the RGDT pin is
asserted when the ring signal is positive or negative.
The output then appears to be twice the frequency of
the ring waveform.
The second method to monitor ring detection uses the
ring detect bits (RDTP, RDTN, and RDT). The RDTP
and RDTN behavior is based on the RNG1-RNG2
voltage. When the signal on RNG1-RNG2 is above the
positive ring threshold, the RDTP bit is set. When the
signal on RNG1-RNG2 is below the negative ring
threshold, the RDTN bit is set. When the signal on
RNG1-RNG2 is between these thresholds, neither bit is
set.
Si3050 + Si3018/19
31