SI3019-F-GSR Silicon Laboratories Inc, SI3019-F-GSR Datasheet - Page 33

• Manufacturer Part Number: SI3019-F-GSR
• Description: IC VOICE DAA GCI/PCM/SPI 16SOIC
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3019-F-GSR

• Function: Data Access Arrangement (DAA)
• Interface: GCI, PCM, SPI
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 8.5mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Includes: Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant

2. The RDTI interrupt fires when a validated ring
3. The INT pin follows the RDTI bit with configurable
4. The RGDT pin can be configured to follow the
5.20. Ringer Impedance and Threshold
The ring detector in a typical DAA is ac coupled to the
line with a large 1  F, 250 V decoupling capacitor. The
ring detector on the Si3018/19 is resistively coupled to
the line. This coupling produces a high ringer
impedance to the line of approximately 20 M  to meet
the majority of country PTT specifications including FCC
and TBR21.
Several countries including Poland, South Africa, and
Slovenia require a maximum ringer impedance that can
be met with an internally-synthesized impedance by
setting the RZ bit (Register 16). Certain countries also
specify ringer thresholds differently. The RT and RT2
bits (Register 16 and Register 17, respectively) select
between three different ringer thresholds: 15 V ±10%,
21 V ±10%, and 45 V ±10%. These three settings
enable
requirements. Thresholds are set so that a ring signal is
guaranteed to not be detected below the minimum, and
a ring signal is guaranteed to be detected above the
maximum.
5.21. Pulse Dialing and Spark Quenching
Pulse dialing is accomplished by going off- and on-hook
to generate make and break pulses. The nominal rate is
10 pulses per second. Some countries have strict
specifications for pulse fidelity including make and
break times, make resistance, and rise and fall times. In
a traditional, solid-state dc holding circuit, there are a
number of issues in meeting these requirements.
The Si3050 dc holding circuit has active control of the
on- and off-hook transients to maintain pulse dialing
fidelity.
Spark quenching requirements in countries, such as
Italy, the Netherlands, South Africa, and Australia, deal
may remain high throughout a distinctive-ring
sequence.
occurs. If RDI is zero (default), the interrupt occurs
on the rising edge of RDT. If RDI is set, the interrupt
occurs on both rising and falling edges of RDT.
polarity.
ringing signal envelope detected by the ring
validation circuit by setting RFWE to 0. If RFWE is
set to 1, the RGDT pin follows an unqualified ring
detect one-shot signal initiated by a ring-threshold
crossing and terminated by a fixed counter timeout
of approximately 5 seconds. (This information is
shown in Register 18).
satisfaction
of
global
ringer
threshold
Rev. 1.31
with the on-hook transition during pulse dialing. These
tests provide an inductive dc feed resulting in a large
voltage spike. This spike is caused by the line
inductance and the sudden decrease in current through
the loop when going on-hook. The traditional way of
dealing with this problem is to put a parallel RC shunt
across the hookswitch relay. The capacitor is large
(~1 µF, 250 V) and relatively expensive. In the Si3050,
loop current can be controlled to achieve three distinct
on-hook speeds to pass spark quenching tests without
additional BOM components. Through the settings of
four bits in three registers, OHS (Register 16), OHS2
(Register 31), SQ0, and SQ1 (Register 59), a slow ramp
down of loop current can be achieved which induces a
delay between the time the OH bit is cleared and the
time the DAA actually goes on-hook.
To ensure proper operation of the DAA during pulse
dialing, disable the automatic resistor calibration that is
performed each time the DAA enters the off-hook state
by setting the RCALD bit (Register 25, bit 5).
5.22. Receive Overload Detection
The Voice DAA chipset is capable of monitoring and
reporting receive overload conditions on the line. Billing
tones, parallel phone off-hook events, polarity reversals
and other disturbances on the line may trigger multiple
levels of overload detection as described below.
Transient events less than 1.1 V
filtered out by the low-pass digital filter on the
Si3050+Si3019. The ROV and ROVI bits are set when
the received signal is greater than 1.1 V
will continue to indicate an overload condition until a
zero is written to clear. The OVL mirrors the function of
the ROV and ROVI bits but it automatically clears after
the overload condition has been removed. When the
OVL
auto-calibration sequence that must complete before
data can be transmitted. An external interrupt can
optionally be triggered by the ROVI bit by setting the
ROVM and INTE bits.
Certain events such as billing tones can be sufficiently
large to disrupt the line-derived power supply of the
Voice DAA line side device (Si3018 or Si3019.) To
ensure that the device maintains the off-hook line state
during these events, the BTE bit should be set. If such
an event occurs while the BTE bit is set, the BTD and
BTDI bits will be asserted. A zero must be written to the
BTE bit to clear the BTD and BTDI bits. An external
interrupt can optionally be triggered by the BTDI bit by
setting the BTDM and INTE bits.
In the event that a line disturbance causes the loop
current to collapse below the minimum required
operating current of the Voice DAA, the DOD and DODI
bit
returns
Si3050 + Si3018/19
to
0,
the
PK
DAA
on the line are
PK
initiates
.
Both bits
an
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