DS3170+ Maxim Integrated Products, DS3170+ Datasheet - Page 158
DS3170+
Manufacturer Part Number
DS3170+
Description
IC TXRX DS3/E3 100-CSBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3170.pdf
(230 pages)
Specifications of DS3170+
Function
Single-Chip Transceiver
Interface
DS3, E3
Number Of Circuits
1
Voltage - Supply
3.135 V ~ 3.465 V
Current - Supply
120mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LBGA
Includes
DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
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Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
Bit 5: Transmit FIFO Overflow Latched (TFOL) – This bit is set when a Transmit FIFO overflow condition occurs.
Bit 4: Transmit FIFO Underflow Latched (TFUL) – This bit is set when a Transmit FIFO underflow condition
occurs. An underflow condition results in a loss of data.
Bit 3: Transmit Packet End Latched (TPEL) – This bit is set when an end of packet is read from the Transmit
FIFO.
Bit 1: Transmit FIFO Empty Latched (TFEL) – This bit is set when the TFE bit transitions from 0 to 1.
Note: This bit is also set when HDLC.TCR.TFRST is deasserted.
Bit 0: Transmit HDLC Data Available Latched (THDAL) – This bit is set when the THDA bit transitions from 0 to
1.
Note: This bit is also set when HDLC.TCR.TFRST is deasserted.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 5: Transmit FIFO Overflow Interrupt Enable (TFOIE) – This bit enables an interrupt if the TFOL bit is set and
the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 4: Transmit FIFO Underflow Interrupt Enable (TFUIE) – This bit enables an interrupt if the TFUL bit is set
and the bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
Bit 3: Transmit Packet End Interrupt Enable (TPEIE) – This bit enables an interrupt if the TPEL bit is set and the
bit in GL.ISRIE.PSRIE[4:1] that corresponds to this port is set.
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
0 = interrupt disabled
1 = interrupt enabled
15
15
--
--
--
--
7
0
7
0
14
14
--
--
--
--
6
0
6
0
HDLC.TSRL
HDLC Transmit Status Register Latched
0A6h
HDLC.TSRIE
HDLC Transmit Status Register Interrupt Enable
0A8h
TFOIE
TFOL
13
13
--
--
5
0
5
0
158 of 230
TFUIE
TFUL
12
12
--
--
4
0
4
0
TPEIE
TPEL
11
11
--
--
3
0
3
0
DS3170 DS3/E3 Single-Chip Transceiver
10
10
--
--
--
--
2
0
2
0
TFEIE
TFEL
--
--
9
1
9
0
1
0
THDAIE
THDAL
--
--
8
0
8
0
0
0
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