DS3170+ Maxim Integrated Products, DS3170+ Datasheet - Page 227
![IC TXRX DS3/E3 100-CSBGA](/photos/6/94/69414/100-csbga_21-0153b_sml.jpg)
DS3170+
Manufacturer Part Number
DS3170+
Description
IC TXRX DS3/E3 100-CSBGA
Manufacturer
Maxim Integrated Products
Datasheet
1.DS3170.pdf
(230 pages)
Specifications of DS3170+
Function
Single-Chip Transceiver
Interface
DS3, E3
Number Of Circuits
1
Voltage - Supply
3.135 V ~ 3.465 V
Current - Supply
120mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LBGA
Includes
DS3 Framers, E3 Framers, HDLC Controller, On-Chip BERTs
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
- Current page: 227 of 230
- Download datasheet (3Mb)
16.6 JTAG Interface AC Characteristics
All AC timing characteristics are specified with a 50 pF capacitive load on JTDO pin and 25 pF capacitive load on
all other digital output pins, V
The voltage threshold for all timing measurements is VDD/2. The generic timing definitions shown in
Figure
Table 16-14. JTAG Interface Timing
(V
Note 1:
Note 2:
Note 3:
JTCLK
JTCLK
JTCLK
JTMS and JTDI
JTMS and JTDI
JTDO
JTDO
JTDO
Any digital output
Any digital output
Any digital output
Any digital output
Any digital output
Any digital output
DD
= 3.3V ±5%, T
NAME(S)
SIGNAL
16-2,
Change during Update-DR state.
Change during Update-IR state to or from EXTEST mode.
Change during Update-IR state to or from HIZ mode.
Figure
j
16-3, and
= -40°C to +125°C.)
SYMBOL
f1
t2
t3
t5
t6
t7
t8
t9
t7
t7
t8
t9
t8
t9
IH
Figure 16-4
= 2.4V and V
Clock Frequency (1/t1)
Clock High or Low Period
Rise/Fall Times
Hold Time from JTCLK Rising Edge
Setup Time to JTCLK Rising Edge
Delay from JTCLK Falling Edge
Delay out of Hi Z from JTCLK Falling Edge
Delay to Hi Z from JTCLK Falling Edge
Delay from JTCLK Falling Edge
Delay from JTCLK Rising Edge
Delay out of Hi Z from JTCLK Falling Edge
Delay into Hi Z from JTCLK Falling Edge
Delay out of Hi Z from JTCLK Rising Edge
Delay into Hi Z from JTCLK Rising Edge
apply to this
IL
DESCRIPTION
= 0.8. The voltage threshold for all timing measurements is VDD/2.
227 of 230
interface.
DS3170 DS3/E3 Single-Chip Transceiver
MIN
20
10
10
0
0
0
0
0
0
0
0
0
0
TYP MAX UNITS NOTES
10
20
20
20
20
20
20
20
20
20
5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure
16-1,
2, 3
2, 3
1
2
1
1
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