SC16C550BIB48,128 NXP Semiconductors, SC16C550BIB48,128 Datasheet - Page 27

• Manufacturer Part Number: SC16C550BIB48,128
• Description: IC UART SINGLE W/FIFO 48-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C550BIB48,128

• Number Of Channels: 1, UART
• Package / Case: 48-LQFP
• Features: Programmable
• Fifo's: 16 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 3 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 4.5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935274388128; SC16C550BIB48-F; SC16C550BIB48-F

NXP Semiconductors
SC16C550B_5
Product data sheet
7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the modem, or
other peripheral device to which the SC16C550B is connected. Four bits of this register
are used to indicate the changed information. These bits are set to a logic 1 whenever a
control input from the modem changes state. These bits are set to a logic 0 whenever the
CPU reads this register.
Table 21.
[1]
Bit
7
6
5
4
3
2
1
0
Whenever any MSR bit 0:3 is set to logic 1, a Modem Status Interrupt will be generated.
Symbol
MSR[7]
MSR[6]
MSR[5]
MSR[4]
MSR[3]
MSR[2]
MSR[1]
MSR[0]
Modem Status Register bits description
Description
Data Carrier Detect. DCD (active HIGH, logical 1). Normally this bit is the
complement of the DCD input. In the loopback mode this bit is equivalent to
the OUT2 bit in the MCR register.
Ring Indicator. RI (active HIGH, logical 1). Normally this bit is the
complement of the RI input. In the loopback mode this bit is equivalent to the
OUT1 bit in the MCR register.
Data Set Ready. DSR (active HIGH, logical 1). Normally this bit is the
complement of the DSR input. In loopback mode this bit is equivalent to the
DTR bit in the MCR register.
Clear To Send. CTS. CTS functions as hardware flow control signal input if it
is enabled via MCR[5]. The transmit holding register flow control is
enabled/disabled by MSR[4]. Flow control (when enabled) allows starting and
stopping the transmissions based on the external modem CTS signal. A logic
1 at the CTS pin will stop SC16C550B transmissions as soon as current
character has finished transmission. Normally MSR[4] is the complement of
the CTS input. However, in the loopback mode, this bit is equivalent to the
RTS bit in the MCR register.
DCD
RI
DSR
CTS
logic 0 = no DCD change (normal default condition)
logic 1 = the DCD input to the SC16C550B has changed state since the last
time it was read. A modem Status Interrupt will be generated.
logic 0 = no RI change (normal default condition).
logic 1 = the RI input to the SC16C550B has changed from a logic 0 to a
logic 1. A modem Status Interrupt will be generated.
logic 0 = no DSR change (normal default condition)
logic 1 = the DSR input to the SC16C550B has changed state since the last
time it was read. A modem Status Interrupt will be generated.
logic 0 = no CTS change (normal default condition)
logic 1 = the CTS input to the SC16C550B has changed state since the last
time it was read. A modem Status Interrupt will be generated.
[1]
Rev. 05 — 1 October 2008
[1]
[1]
[1]
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
SC16C550B
© NXP B.V. 2008. All rights reserved.
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