SC16IS750IBS,151 NXP Semiconductors, SC16IS750IBS,151 Datasheet - Page 10

IC UART I2C/SPI 24-HVQFN

SC16IS750IBS,151

Manufacturer Part Number
SC16IS750IBS,151
Description
IC UART I2C/SPI 24-HVQFN
Manufacturer
NXP Semiconductors
Type
IrDA or RS- 232 or RS- 485r
Datasheet

Specifications of SC16IS750IBS,151

Number Of Channels
1, UART
Package / Case
24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
Features
Low Current
Fifo's
64 Byte
Protocol
RS232, RS485
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Data Rate
5 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.3 V
Supply Current
6 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.5 V or 3.3 V
Transmit Fifo
64Byte
Receive Fifo
64Byte
Transmitter And Receiver Fifo Counter
No
Operating Supply Voltage (max)
3.6V
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-2234
935279271151
SC16IS750IBS-S
NXP Semiconductors
SC16IS740_750_760_6
Product data sheet
Fig 9.
(1) N = receiver FIFO trigger level.
(2) The two blocks in dashed lines cover the case where an additional character is sent, as described in
RTS functional timing
receive
FIFO
RTS
read
RX
7.2.1 Auto RTS
Figure 9
are stored in the TCR or FCR. RTS is active if the RX FIFO level is below the halt trigger
level in TCR[3:0]. When the receiver FIFO halt trigger level is reached, RTS is deasserted.
The sending device (for example, another UART) may send an additional character after
the trigger level is reached (assuming the sending UART has another character to send)
because it may not recognize the deassertion of RTS until it has begun sending the
additional character. RTS is automatically reasserted once the receiver FIFO reaches the
resume trigger level programmed via TCR[7:4]. This reassertion allows the sending
device to resume transmission.
start
Fig 8.
character
shows RTS functional timing. The receiver FIFO trigger levels used in auto RTS
N
Autoflow control (auto RTS and auto CTS) example
FIFO
FIFO
TX
RX
stop
UART 1
Single UART with I
SERIAL TO
TO SERIAL
PARALLEL
PARALLEL
CONTROL
CONTROL
Rev. 06 — 13 May 2008
FLOW
FLOW
start
character
N + 1
1
RTS
CTS
RX
TX
2
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
stop
SC16IS740/750/760
TX
CTS
RX
RTS
TO SERIAL
SERIAL TO
PARALLEL
N
PARALLEL
CONTROL
CONTROL
FLOW
FLOW
UART 2
N + 1
Section 7.2.1
© NXP B.V. 2008. All rights reserved.
002aab040
start
FIFO
FIFO
RX
TX
002aab656
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