SC16IS750IBS,151 NXP Semiconductors, SC16IS750IBS,151 Datasheet - Page 34
![IC UART I2C/SPI 24-HVQFN](/photos/6/82/68224/568-24-hvqfn_sot616-1_sml.jpg)
SC16IS750IBS,151
Manufacturer Part Number
SC16IS750IBS,151
Description
IC UART I2C/SPI 24-HVQFN
Manufacturer
NXP Semiconductors
Type
IrDA or RS- 232 or RS- 485r
Datasheet
1.SC16IS740IPW112.pdf
(62 pages)
Specifications of SC16IS750IBS,151
Number Of Channels
1, UART
Package / Case
24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
Features
Low Current
Fifo's
64 Byte
Protocol
RS232, RS485
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Data Rate
5 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.3 V
Supply Current
6 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.5 V or 3.3 V
Transmit Fifo
64Byte
Receive Fifo
64Byte
Transmitter And Receiver Fifo Counter
No
Operating Supply Voltage (max)
3.6V
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-2234
935279271151
SC16IS750IBS-S
935279271151
SC16IS750IBS-S
NXP Semiconductors
SC16IS740_750_760_6
Product data sheet
8.19 I/O Control register (IOControl)
This register is only available on the SC16IS750 and SC16IS760.
Table 30.
Remark: As I/O pins, the direction, state, and interrupt of GPIO4 to GPIO7 are controlled
by the following registers: IODir, IOState, IOIntEna, and IOControl. The state of CD, RI,
DSR pins will not be reflected in MSR[7:5] or MSR[3:1], and any change of state on these
three pins will not trigger a modem status interrupt (even if enabled via IER[3]), and the
state of the DTR pin cannot be controlled by MCR[0].
As modem CD, RI, DSR pins, the status at the input of these three pins can be read from
MSR[7:5] and MSR[3:1], and the state of DTR pin can be controlled by MCR[0]. Also, if
modem status interrupt bit is enabled, IER[3], a change of state of RI, CD, DSR pins will
trigger a modem interrupt. Bit[7:4] of the IODir, IOState, and IOIntEna registers will not
have any effect on these three pins.
Bit
7:4
3
2
1
0
Symbol
-
SRESET
-
GPIO[7:4] or
modem pins
IOLATCH
IOControl register bits description
Single UART with I
Rev. 06 — 13 May 2008
Description
reserved for future use
software reset
reserved for future use
This bit programs GPIO[7:4] as I/O pins or modem RI, CD, DTR, DSR
pins.
enable/disable inputs latching
A write to bit will reset the device. Once the device is reset this bit is
automatically set to ‘0’
0 = GPIO[7:4] behave as I/O pins
1 = GPIO[7:4] behave as RI, CD, DTR, DSR
0 = input values are not latched. A change in any input generates an
interrupt. A read of the input register clears the interrupt. If the input
goes back to its initial logic state before the input register is read,
then the interrupt is cleared.
1 = input values are latched. A change in the input generates an
interrupt and the input logic value is loaded in the bit of the
corresponding input state register (IOState). A read of the IOState
register clears the interrupt. If the input pin goes back to its initial
logic state before the interrupt register is read, then the interrupt is
not cleared and the corresponding bit of the IOState register keeps
the logic value that initiates the interrupt.
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
SC16IS740/750/760
© NXP B.V. 2008. All rights reserved.
34 of 62