SC16IS750IBS,151 NXP Semiconductors, SC16IS750IBS,151 Datasheet - Page 38
![IC UART I2C/SPI 24-HVQFN](/photos/6/82/68224/568-24-hvqfn_sot616-1_sml.jpg)
SC16IS750IBS,151
Manufacturer Part Number
SC16IS750IBS,151
Description
IC UART I2C/SPI 24-HVQFN
Manufacturer
NXP Semiconductors
Type
IrDA or RS- 232 or RS- 485r
Datasheet
1.SC16IS740IPW112.pdf
(62 pages)
Specifications of SC16IS750IBS,151
Number Of Channels
1, UART
Package / Case
24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
Features
Low Current
Fifo's
64 Byte
Protocol
RS232, RS485
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Data Rate
5 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
2.3 V
Supply Current
6 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.5 V or 3.3 V
Transmit Fifo
64Byte
Receive Fifo
64Byte
Transmitter And Receiver Fifo Counter
No
Operating Supply Voltage (max)
3.6V
Mounting
Surface Mount
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-2234
935279271151
SC16IS750IBS-S
935279271151
SC16IS750IBS-S
NXP Semiconductors
SC16IS740_750_760_6
Product data sheet
Fig 18. Data transfer on the I
Fig 19. Acknowledge on the I
SDA
SCL
condition
SCL from master
START
by transmitter
S
data output
data output
by receiver
10.2 Addressing and transfer formats
MSB
A slave receiver must generate an acknowledge after the reception of each byte, and a
master must generate one after the reception of each byte clocked out of the slave
transmitter.
There are two exceptions to the ‘acknowledge after every byte’ rule. The first occurs when
a master is a receiver: it must signal an end of data to the transmitter by not signalling an
acknowledge on the last byte that has been clocked out of the slave. The acknowledge
related clock, generated by the master should still take place, but the SDA line will not be
pulled down. In order to indicate that this is an active and intentional lack of
acknowledgement, we shall term this special condition as a ‘negative acknowledge’.
The second exception is that a slave will send a negative acknowledge when it can no
longer accept additional data bytes. This occurs after an attempted transfer that cannot be
accepted.
Each device on the bus has its own unique address. Before any data is transmitted on the
bus, the master transmits on the bus the address of the slave to be accessed for this
transaction. A well-behaved slave with a matching address, if it exists on the network,
should of course acknowledge the master's addressing. The addressing is done by the
first byte transmitted by the master after the START condition.
0
condition
START
S
1
2
2
C-bus
C-bus
interrupt within receiver
0
6
byte complete,
Single UART with I
Rev. 06 — 13 May 2008
1
7
ACK
8
acknowledgement signal
from receiver
6
7
2
0
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
clock line held LOW
while interrupt is serviced
8
1
002aab013
SC16IS740/750/760
2 to 7
transmitter stays off of the bus
during the acknowledge clock
acknowledgement signal
from receiver
ACK
8
© NXP B.V. 2008. All rights reserved.
condition
STOP
P
002aab012
38 of 62