SC16C752BIBS,128 NXP Semiconductors, SC16C752BIBS,128 Datasheet - Page 29

• Manufacturer Part Number: SC16C752BIBS,128
• Description: IC DUAL UART 64BYTE 32HVQFN
• Manufacturer: NXP Semiconductors

Specifications of SC16C752BIBS,128

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935276389128; SC16C752BIBS-F; SC16C752BIBS-F

NXP Semiconductors
SC16C752B
Product data sheet
7.12 Transmission Control Register (TCR)
7.11 Divisor latches (DLL, DLM)
Table 19.
These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock
in the baud rate generator. DLM stores the most significant part of the divisor. DLL stores
the least significant part of the divisor.
Note that DLL and DLM can only be written to before Sleep mode is enabled, i.e., before
IER[4] is set.
This 8-bit register is used to store the receive FIFO threshold levels to stop/start
transmission during hardware/software flow control.
Register bit settings.
Table 20.
TCR trigger levels are available from 0 bytes to 60 bytes with a granularity of four.
Remark: TCR can only be written to when EFR[4] = logic 1 and MCR[6] = logic 1. The
programmer must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in
hardware check to make sure this condition is met. Also, the TCR must be programmed
with this condition before auto-RTS or software flow control is enabled to avoid spurious
operation of the device.
Bit
5
4
3:0
Bit
7:4
3:0
Symbol
EFR[5]
EFR[4]
EFR[3:0] Combinations of software flow control can be selected by programming these bits.
Symbol
TCR[7:4]
TCR[3:0]
Enhanced Feature Register bits description
Transmission Control Register bits description
Description
Special character detect.
Enhanced functions enable bit.
See
All information provided in this document is subject to legal disclaimers.
logic 0 = special character detect disabled (normal default condition)
logic 1 = special character detect enabled. Received data is compared with
Xoff2 data. If a match occurs, the received data is transferred to FIFO and IIR[4]
is set to a logic 1 to indicate a special character has been detected.
logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4],
MCR[7:5]
logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5] can
be modified, i.e., this bit is therefore a write enable.
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
Table 3 “Software flow control options
Description
receive FIFO trigger level to resume transmission (0 to 60).
receive FIFO trigger level to halt transmission (0 to 60).
Rev. 6 — 30 November 2010
Table 20
…continued
(EFR[0:3])”.
shows Transmission Control
SC16C752B
© NXP B.V. 2010. All rights reserved.
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