SC28L91A1B,528 NXP Semiconductors, SC28L91A1B,528 Datasheet - Page 12
![IC UART SINGLE W/FIFO 44PQFP](/photos/6/62/66269/568-44-qfp_sot307-2_sml.jpg)
SC28L91A1B,528
Manufacturer Part Number
SC28L91A1B,528
Description
IC UART SINGLE W/FIFO 44PQFP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Datasheet
1.SC28L91A1A529.pdf
(43 pages)
Specifications of SC28L91A1B,528
Features
False-start Bit Detection
Number Of Channels
1, UART
Fifo's
16 Byte
Voltage - Supply
3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
44-MQFP, 44-PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935267419528
SC28L91A1B-T
SC28L91A1B-T
SC28L91A1B-T
SC28L91A1B-T
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC28L91A1B,528
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
SC28L91A1B,528
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
Philips Semiconductors
AC CHARACTERISTICS (5 VOLT)
V
2004 Oct 21
Symbol
Reset Timing (See Figure 4)
t
Bus Timing
t
t
t
t
t
t
t
t
t
t
t
t
Port Timing
t
t
t
Interrupt Timing (See Figure 10)
t
Clock Timing (See Figure 11)
t
f
f
f
t
f
t
f
Transmitter Timing, external clock (See Figure 12)
t
t
CC
RES
*AS
*AH
*CS
*CH
*RW
*DD
*DA
*DF
*DI
*DS
*DH
*RWD
*PS
*PH
*PD
*IR
*CLK
*CLK
*CTC
*CTC
*RX
*RX
*TX
*TX
*TXD
*TCS
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
= 5.0 V
5
5
10 %, T
(See Figure 5)
(See Figure 9)
Parameter
Reset pulse width
A0–A3 setup time to RDN, WRN Low
A0–A3 hold time from RDN, WRN low
CEN setup time to RDN, WRN low
CEN Hold time from RDN. WRN low
WRN, RDN pulse width (Low time)
Data valid after RDN low (125pF load. See Figure 3 for smaller loads.)
RDN low to data bus active
Data bus floating after RDN or CEN high
RDN or CEN high to data bus invalid
Data bus setup time before WRN or CEN high (write cycle)
Data hold time after WRN high
High time between read and/or write cycles
Port in setup time before RDN low (Read IP ports cycle)
Port in hold time after RDN high
OP port valid after WRN or CEN high (OPR write cycle)
INTRN (or OP3–OP7 when used as interrupts) negated from:
X1/CLK high or low time
X1/CLK frequency
C/T Clk (IP2) high or low time (C/T external clock input)
C/T Clk (IP2) frequency
RxC high or low time (16X)
RxC Frequency (16X)(for higher speeds contact factory)
RxC Frequency (1x)
TxC High or low time (16X)
TxC frequency (16X) (for higher speeds contact factory)
TxC frequency (1X)
TxD output delay from TxC low (TxC input pin)
Output delay from TxC output pin low to TxD data output
Read RxFIFO (RxRDY/FFULL interrupt)
Write TxFIFO (TxRDY interrupt)
Reset Command (delta break change interrupt)
Stop C/T command (Counter/timer interrupt
Read IPCR (delta input port change interrupt)
Write IMR (Clear of change interrupt mask bit(s))
amb
= –40 C to +85 C, unless otherwise specified.
8
8, 9
(for higher speeds contact factory)
8, 9
8
(for higher speeds contact factory)
6
1, 2, 3, 4
7
5, 7
12
Min
100
10
20
0
0
15
0
0
25
0
17
0
0
30
0.1
30
0
30
0
0
30
0
Typ
18
6
12
8
40
–12
–20
–20
40
40
40
40
40
40
40
20
3.686
10
10
10
40
6
Max
55
20
60
60
60
60
60
60
60
8.0
8.0
16
1
16
1
60
30
SC28L91
Product data sheet
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz
ns
ns