SC28L91A1B,528 NXP Semiconductors, SC28L91A1B,528 Datasheet - Page 34
![IC UART SINGLE W/FIFO 44PQFP](/photos/6/62/66269/568-44-qfp_sot307-2_sml.jpg)
SC28L91A1B,528
Manufacturer Part Number
SC28L91A1B,528
Description
IC UART SINGLE W/FIFO 44PQFP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Datasheet
1.SC28L91A1A529.pdf
(43 pages)
Specifications of SC28L91A1B,528
Features
False-start Bit Detection
Number Of Channels
1, UART
Fifo's
16 Byte
Voltage - Supply
3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
44-MQFP, 44-PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935267419528
SC28L91A1B-T
SC28L91A1B-T
SC28L91A1B-T
SC28L91A1B-T
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC28L91A1B,528
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
SC28L91A1B,528
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
Philips Semiconductors
NOTE:
2004 Oct 21
3.3 V or 5.0 V Universal Asynchronous
Receiver/Transmitter (UART)
For Figures 6 and 7 WRN changing within the time of CEN low may cause short read or write pulses that could upset internal pointers and
registers. Bus action terminates on the rise of CEN or the fall of DACKN, which ever occurs first.
NOTE: DACKN low requires two rising edges of X1 clock after CSN is low.
NOTE: DACKN low requires two rising edges of X1 clock after CSN is low.
DTACKN
X1/CLK
DTACKN
D0–D7
A1–A4
X1/CLK
D0–D7
RWN
A1–A4
CSN
RWN
CSN
t
DA
Figure 6. Bus Timing (Read Cycle) (68XXX mode)
Figure 7. Bus Timing (Write Cycle) (68XXX mode)
t
t
AS
AS
t
CS
t
VALID
CS
t
t
NOT
CSC
DD
t
t
DS
CSC
t
AH
t
AH
t
DCW
t
DCR
34
DATA VALID
t
DAT
t
DAT
t
RWD
t
RWD
t
t
t
CH
t
CH
t
DAH
t
DF
DH
DAH
SD00687
SD00688
SC28L91
Product data sheet