SC16C654BIBM,151 NXP Semiconductors, SC16C654BIBM,151 Datasheet - Page 19

• Manufacturer Part Number: SC16C654BIBM,151
• Description: IC UART QUAD W/FIFO 64-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C654BIBM,151

• Features: False-start Bit Detection
• Number Of Channels: 4, QUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3278; 935279068151; SC16C654BIBM-S

Philips Semiconductors
9397 750 14965
Product data sheet
6.6 Special feature software flow control
6.7 Xon any feature
6.8 Hardware/software and time-out interrupts
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software flow control.
Different conditions can be set to detect Xon/Xoff characters and suspend/resume
transmissions. When double 8-bit Xon/Xoff characters are selected, the
SC16C654B/654DB compares two consecutive receive characters with two software flow
control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly.
Under the above described flow control mechanisms, flow control characters are not
placed (stacked) in the user accessible RX data buffer or FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed, the
SC16C654B/654DB automatically sends an Xoff message (when enabled) via the serial
TX output to the remote modem. The SC16C654B/654DB sends the Xoff1,2 characters
as soon as received data passes the programmed trigger level. To clear this condition, the
SC16C654B/654DB will transmit the programmed Xon1,2 characters as soon as receive
data drops below the programmed trigger level.
A special feature is provided to detect an 8-bit character when EFR[5] is set. When 8-bit
character is detected, it will be placed on the user-accessible data stack along with normal
incoming RX data. This condition is selected in conjunction with EFR[0:3]. Note that
software flow control should be turned off when using this special mode by setting
EFR[0:3] to a logic 0.
The SC16C654B/654DB compares each incoming receive character with Xoff2 data. If a
match exists, the received data will be transferred to the FIFO, and ISR[4] will be set to
indicate detection of a special character. Although the Internal Register Table
shows each X-Register with eight bits of character information, the actual number of bits is
dependent on the programmed word length. Line Control Register bits LCR[0:1] define the
number of character bits, that is, either 5 bits, 6 bits, 7 bits or 8 bits. The word length
selected by LCR[0:1] also determine the number of bits that will be used for the special
character comparison. Bit 0 in the X-registers corresponds with the LSB bit for the receive
character.
A special feature is provided to return the Xoff flow control to the inactive state following its
activation. In this mode, any RX character received will return the Xoff flow control to the
inactive state so that transmissions may be resumed with a remote buffer. This feature is
more fully defined in
Three special interrupts have been added to monitor the hardware and software flow
control. The interrupts are enabled by IER[5:7]. Care must be taken when handling these
interrupts. Following a reset, the transmitter interrupt is enabled, the SC16C654B/654DB
will issue an interrupt to indicate that the Transmit Holding Register is empty. This interrupt
must be serviced prior to continuing operations. The LSR register provides the current
singular highest priority interrupt only. It could be noted that CTS and RTS interrupts have
lowest interrupt priority. A condition can exist where a higher priority interrupt may mask
the lower priority CTS/RTS interrupt(s). Only after servicing the higher pending interrupt
will the lower priority CTS/TRS interrupt(s) be reflected in the status register. Servicing the
interrupt without investigating further interrupt conditions can result in data errors.
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Section 6.5 “Software flow
Rev. 02 — 20 June 2005
control”.
SC16C654B/654DB
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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