SC16C654BIA68,512 NXP Semiconductors, SC16C654BIA68,512 Datasheet - Page 29

• Manufacturer Part Number: SC16C654BIA68,512
• Description: ID QUAD UART 64BYTE 68PLCC
• Manufacturer: NXP Semiconductors

Specifications of SC16C654BIA68,512

• Features: False-start Bit Detection
• Number Of Channels: 4, QUART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 68-LCC (J-Lead)
• Transmit Fifo: 64Byte
• Receive Fifo: 64Byte
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Package Type: PLCC
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935274935512; SC16C654BIA68; SC16C654BIA68

Philips Semiconductors
9397 750 14965
Product data sheet
7.4 Interrupt Status Register (ISR)
The SC16C654B/654DB provides six levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with six
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged until
the pending interrupt is serviced. Whenever the interrupt status register is read, the
interrupt status is cleared. However, it should be noted that only the current pending
interrupt is cleared by the read. A lower level interrupt may be seen after re-reading the
interrupt status bits.
prioritized interrupt levels and the interrupt sources associated with each of these interrupt
levels.
Table 13:
Table 14:
Priority
level
1
2
2
3
4
5
6
Bit
7:6
5:4
3:1
0
Interrupt source
Interrupt Status Register bits description
ISR[5]
0
0
0
0
0
0
1
Symbol
ISR[7:6]
ISR[5:4]
ISR[3:1]
ISR[0]
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
ISR[4]
0
0
0
0
0
1
0
Table 13 “Interrupt source”
Rev. 02 — 20 June 2005
Description
FIFOs enabled. These bits are set to a logic 0 when the FIFO is not
being used. They are set to a logic 1 when the FIFOs are enabled.
INT priority bits 4:3. These bits are enabled when EFR[4] is set to a
logic 1. ISR[4] indicates that matching Xoff character(s) have been
detected. ISR[5] indicates that CTS, RTS have been generated. Note
that once set to a logic 1, the ISR[4] bit will stay a logic 1 until Xon
character(s) are received.
INT priority bits 2:0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3; see
INT status.
logic 0 or cleared = default condition
logic 0 or cleared = default condition
Logic 0 or cleared = default condition.
logic 0 = an interrupt is pending and the ISR contents may be used as
a pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
ISR[3]
0
0
1
0
0
0
0
ISR[2]
1
1
1
0
0
0
0
ISR[1]
1
0
0
1
0
0
0
shows the data values (bits 0:5) for the six
SC16C654B/654DB
ISR[0]
0
0
0
0
0
0
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Source of the interrupt
LSR (Receiver Line Status
Register)
RXRDY (Receive Data
Ready)
RXRDY (Receive Data
time-out)
TXRDY (Transmitter Holding
Register Empty)
MSR (Modem Status
Register)
RXRDY (Received Xoff
signal)/Special character
CTS, RTS change of state
Table
13.
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