SC16C750BIB64,157 NXP Semiconductors, SC16C750BIB64,157 Datasheet - Page 16

• Manufacturer Part Number: SC16C750BIB64,157
• Description: IC UART 64BYTE 64LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C750BIB64,157

• Number Of Channels: 1, UART
• Package / Case: 64-LQFP
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 3 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current: 4.5 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V or 3.3 V or 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935274403157; SC16C750BIB64; SC16C750BIB64

NXP Semiconductors
SC16C750B_5
Product data sheet
7.1 Transmit Holding Register (THR) and Receive Holding Register (RHR)
7.2 Interrupt Enable Register (IER)
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the
THR, providing that the THR or TSR is empty. The THR empty flag in the LSR register will
be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR.
Note that a write operation can be performed when the THR empty flag is set
(logic 0 = FIFO full; logic 1 = at least one FIFO location available).
The serial receive section also contains an 8-bit Receive Holding Register (RHR).
Receive data is removed from the SC16C750B and receive FIFO by reading the RHR
register. The receive section provides a mechanism to prevent false starts. On the falling
edge of a start or false start bit, an internal receiver counter starts counting clocks at the
16 clock rate. After 7
start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated.
Evaluating the start bit in this manner prevents the receiver from assembling a false
character. Receiver status codes will be posted in the LSR.
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INT output pin.
Table 9.
Bit
7:6
5
4
3
2
Symbol
IER[7:6]
IER[5]
IER[4]
IER[3]
IER[2]
Interrupt Enable Register bits description
Description
Not used.
Low power mode.
Sleep mode.
Modem Status Interrupt.
Receive Line Status interrupt. This interrupt will be issued whenever a fully
assembled receive character is transferred from RSR to the RHR/FIFO, i.e.,
data ready, LSR[0].
logic 0 = disable Low power mode (normal default condition)
logic 1 = enable Low power mode
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode. See
logic 0 = disable the modem status register interrupt (normal default
condition)
logic 1 = enable the modem status register interrupt
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
1
Rev. 05 — 17 October 2008
2
clocks, the start bit time should be shifted to the center of the
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
Section 6.7 “Sleep mode”
SC16C750B
© NXP B.V. 2008. All rights reserved.
for details.
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