SC28L201A1DGG,112 NXP Semiconductors, SC28L201A1DGG,112 Datasheet - Page 45
SC28L201A1DGG,112
Manufacturer Part Number
SC28L201A1DGG,112
Description
IC UART W/FIFO 48-TSSOP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Datasheet
1.SC28L201A1DGG118.pdf
(110 pages)
Specifications of SC28L201A1DGG,112
Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
256 Byte
Voltage - Supply
3.3V, 5V
With Parallel Port
Yes
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3293-5
935277824112
SC28L201A1DGG
935277824112
SC28L201A1DGG
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Philips Semiconductors
9397 750 13138
Product data sheet
Table 17:
Bit
4:3
2
1:0
Symbol
MR1 - Mode Register 1 (address 0x21) bit description
Description
Parity Mode Select
If ‘with parity’ or ‘force parity’ is selected, a parity bit is added to the
transmitted character and the receiver performs a parity check on incoming
data. MR1[4:3] = 11 selects the channel to operate in the special Wake-up
mode.
Parity Type Select
This bit sets the parity type (odd or even) if the ‘with parity’ mode is
programmed by MR1[4:3], and the polarity of the forced parity bit if the ‘force
parity mode is programmed it has no effect if the ‘no parity’ mode is
programmed. In the special ‘Wake-up’ mode, it selects the polarity of the A/D
bit. The parity bit is used to an address or data byte in the ‘Wake-up’ mode.
Bits per Character Select.
This field selects the number of data bits per character to be transmitted and
received. This number does not include the start, parity, or stop bits.
00 = with parity
01 = force parity
10 = no parity
11 = multi-drop Special Mode
0 = even
1 = odd
00 = 5 bits
01 = 6 bits
10 = 7 bits
11 = 8 bits
Rev. 01 — 31 October 2005
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
…continued
SC28L201
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