C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 210

• Manufacturer Part Number: C8051F502-IMR
• Description: MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F502-IMR

• Package: 32QFN EP
• Device Core: 8051
• Family Name: C8051F50x
• Maximum Speed: 50 MHz
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/UART
• On-chip Adc: 32-chx12-bit
• Operating Temperature: -40 to 125 °C
• Number Of Timers: 4

Note: These registers are used in both master and slave mode. The register bits marked with (m) are accessible only in
LIN0CTRL
LIN0SIZE
LIN0ERR
LIN0MUL
C8051F50x/F51x
21.7.2. LIN Indirect Access SFR Registers Definitions
Table 21.4 lists the 15 indirect registers used to configured and communicate with the LIN controller.
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LIN0DT1
LIN0DT2
LIN0DT3
LIN0DT4
LIN0DT5
LIN0DT6
LIN0DT7
LIN0DT8
LIN0DIV
LIN0ST
LIN0ID
Name
Master mode while the register bits marked with (s) are accessible only in slave mode. All other registers are
accessible in both modes.
Address
0x0A
0x0B
0x0C
0x0D
0x0E
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
ENHCHK
STOP(s)
ACTIVE
Table 21.4. LIN Registers (Indirectly Addressable)
Bit7
PRESCL[1:0]
SLEEP(s)
IDLTOUT ABORT(s) DTREQ(s)
Bit6
TXRX
Bit5
ID5
Rev. 1.2
SYNCH(s) PRTY(s)
DTACK(s)
Bit4
ID4
DIVLSB[7:0]
DATA1[7:0]
DATA2[7:0]
DATA3[7:0]
DATA4[7:0]
DATA5[7:0]
DATA7[7:0]
DATA8[7:0]
DATA67:0]
LINMUL[4:0]
RSTINT RSTERR WUPREQ STREQ(m)
LININT
Bit3
ID3
ERROR
TOUT
Bit2
ID2
LINSIZE[3:0]
WAKEUP
Bit1
CHK
ID1
BITERR
DONE
DIV9
Bit0
ID0