C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 241
C8051F502-IMR
Manufacturer Part Number
C8051F502-IMR
Description
MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F502-IM.pdf
(312 pages)
Specifications of C8051F502-IMR
Package
32QFN EP
Device Core
8051
Family Name
C8051F50x
Maximum Speed
50 MHz
Ram Size
4.25 KB
Program Memory Size
64 KB
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
25
Interface Type
I2C/SPI/UART
On-chip Adc
32-chx12-bit
Operating Temperature
-40 to 125 °C
Number Of Timers
4
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Values Read
1110
1100 0 0
1000 1
0
0 0
0 X A master START was gener-
0 X A master data byte was
0 A master data or address byte
1
Current SMbus State
ated.
was transmitted; NACK
received.
A master data or address byte
was transmitted; ACK
received.
received; ACK requested.
Table 23.4. SMBus Status Decoding
Rev. 1.2
Typical Response Options
Load slave address + R/W into
SMB0DAT.
Set STA to restart transfer.
Abort transfer.
Load next data byte into
SMB0DAT.
End transfer with STOP.
End transfer with STOP and start
another transfer.
Send repeated START.
Switch to Master Receiver Mode
(clear SI without writing new data
to SMB0DAT).
Acknowledge received byte;
Read SMB0DAT.
Send NACK to indicate last byte,
and send STOP.
Send NACK to indicate last byte,
and send STOP followed by
START.
Send ACK followed by repeated
START.
Send NACK to indicate last byte,
and send repeated START.
Send ACK and switch to Master
Transmitter Mode (write to
SMB0DAT before clearing SI).
Send NACK and switch to Mas-
ter Transmitter Mode (write to
SMB0DAT before clearing SI).
C8051F50x/F51x
Values to
Write
0
1
0
0
0
1
1 0 X
0
0
0
1
1
1
0 0 1
0 0 0
0 X 1100
0 X
1 X
0 X 1100
1 X
1 X
0 X 1000
0 1
1 0
1 0
0 1
0 0
1000
1100
1100
1110
1110
1110
1110
1110
—
—
—
—
241
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