C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 6

• Manufacturer Part Number: C8051F502-IMR
• Description: MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F502-IMR

• Package: 32QFN EP
• Device Core: 8051
• Family Name: C8051F50x
• Maximum Speed: 50 MHz
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/UART
• On-chip Adc: 32-chx12-bit
• Operating Temperature: -40 to 125 °C
• Number Of Timers: 4

C8051F50x/F51x
22. Controller Area Network (CAN0) ........................................................................ 218
23. SMBus................................................................................................................... 226
24. UART0 ................................................................................................................... 243
25. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 252
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21.5. Sleep Mode and Wake-Up ............................................................................ 207
21.6. Error Detection and Handling ........................................................................ 207
21.7. LIN Registers................................................................................................. 208
22.1. Bosch CAN Controller Operation................................................................... 219
22.2. CAN Registers............................................................................................... 222
23.1. Supporting Documents .................................................................................. 227
23.2. SMBus Configuration..................................................................................... 227
23.3. SMBus Operation .......................................................................................... 227
23.4. Using the SMBus........................................................................................... 229
23.5. SMBus Transfer Modes................................................................................. 236
23.6. SMBus Status Decoding................................................................................ 240
24.1. Baud Rate Generator .................................................................................... 243
24.2. Data Format................................................................................................... 245
24.3. Configuration and Operation ......................................................................... 246
25.1. Signal Descriptions........................................................................................ 253
21.7.1. LIN Direct Access SFR Registers Definitions ....................................... 208
21.7.2. LIN Indirect Access SFR Registers Definitions ..................................... 210
22.1.1. CAN Controller Timing .......................................................................... 219
22.1.2. CAN Register Access............................................................................ 220
22.1.3. Example Timing Calculation for 1 Mbit/Sec Communication ................ 220
22.2.1. CAN Controller Protocol Registers........................................................ 222
22.2.2. Message Object Interface Registers ..................................................... 222
22.2.3. Message Handler Registers.................................................................. 222
22.2.4. CAN Register Assignment .................................................................... 223
23.3.1. Transmitter vs. Receiver ....................................................................... 228
23.3.2. Arbitration.............................................................................................. 228
23.3.3. Clock Low Extension............................................................................. 228
23.3.4. SCL Low Timeout.................................................................................. 228
23.3.5. SCL High (SMBus Free) Timeout ......................................................... 229
23.4.1. SMBus Configuration Register.............................................................. 229
23.4.2. SMB0CN Control Register .................................................................... 233
23.4.3. Data Register ........................................................................................ 236
23.5.1. Write Sequence (Master) ...................................................................... 237
23.5.2. Read Sequence (Master) ...................................................................... 238
23.5.3. Write Sequence (Slave) ........................................................................ 239
23.5.4. Read Sequence (Slave) ........................................................................ 240
24.3.1. Data Transmission ................................................................................ 246
24.3.2. Data Reception ..................................................................................... 246
24.3.3. Multiprocessor Communications ........................................................... 247
25.1.1. Master Out, Slave In (MOSI)................................................................. 253
25.1.2. Master In, Slave Out (MISO)................................................................. 253
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