C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 240
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C8051F502-IMR
Manufacturer Part Number
C8051F502-IMR
Description
MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F502-IM.pdf
(312 pages)
Specifications of C8051F502-IMR
Package
32QFN EP
Device Core
8051
Family Name
C8051F50x
Maximum Speed
50 MHz
Ram Size
4.25 KB
Program Memory Size
64 KB
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
25
Interface Type
I2C/SPI/UART
On-chip Adc
32-chx12-bit
Operating Temperature
-40 to 125 °C
Number Of Timers
4
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C8051F50x/F51x
23.5.4. Read Sequence (Slave)
During a read sequence, an SMBus master reads data from a slave device. The slave in this transfer will
be a receiver during the address byte, and a transmitter during all data bytes. When slave events are
enabled (INH = 0), the interface enters Slave Receiver Mode (to receive the slave address) when a START
followed by a slave address and direction bit (READ in this case) is received. Upon entering Slave
Receiver Mode, an interrupt is generated and the ACKRQ bit is set. The software must respond to the
received slave address with an ACK, or ignore the received slave address with a NACK. The interrupt will
occur after the ACK cycle.
If the received slave address is ignored, slave interrupts will be inhibited until the next START is detected.
If the received slave address is acknowledged, zero or more data bytes are transmitted. If the received
slave address is acknowledged, data should be written to SMB0DAT to be transmitted. The interface
enters Slave Transmitter Mode, and transmits one or more bytes of data. After each byte is transmitted, the
master sends an acknowledge bit; if the acknowledge bit is an ACK, SMB0DAT should be written with the
next data byte. If the acknowledge bit is a NACK, SMB0DAT should not be written to before SI is cleared
(Note: an error condition may be generated if SMB0DAT is written following a received NACK while in
Slave Transmitter Mode). The interface exits Slave Transmitter Mode after receiving a STOP. Note that the
interface will switch to Slave Receiver Mode if SMB0DAT is not written following a Slave Transmitter inter-
rupt. Figure 23.8 shows a typical slave read sequence. Two transmitted data bytes are shown, though any
number of bytes may be transmitted. Notice that all of the ‘data byte transferred’ interrupts occur after the
ACK cycle in this mode.
23.6. SMBus Status Decoding
The current SMBus status can be easily decoded using the SMB0CN register. In the tables, STATUS
VECTOR refers to the four upper bits of SMB0CN: MASTER, TXMODE, STA, and STO. The shown
response options are only the typical responses; application-specific procedures are allowed as long as
they conform to the SMBus specification. Highlighted responses are allowed by hardware but do not con-
form to the SMBus specification.
240
S
Received by SMBus
Interface
Transmitted by
SMBus Interface
SLA
Figure 23.8. Typical Slave Read Sequence
R
A
Data Byte
Rev. 1.2
Interrupts
A
S = START
P = STOP
N = NACK
R = READ
SLA = Slave Address
Data Byte
N
P
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