C8051F502-IMR Silicon Laboratories Inc, C8051F502-IMR Datasheet - Page 212

• Manufacturer Part Number: C8051F502-IMR
• Description: MCU 8-Bit C8051F50x 8051 CISC 64KB Flash 2.5V/3.3V/5V 32-Pin QFN EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F502-IMR

• Package: 32QFN EP
• Device Core: 8051
• Family Name: C8051F50x
• Maximum Speed: 50 MHz
• Ram Size: 4.25 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 2.5|3.3|5 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 25
• Interface Type: I2C/SPI/UART
• On-chip Adc: 32-chx12-bit
• Operating Temperature: -40 to 125 °C
• Number Of Timers: 4

C8051F50x/F51x
LIN Register Definition 21.5. LIN0CTRL: LIN0 Control Register
Indirect Address = 0x08
212
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
WUPREQ
RSTERR
RSTINT
STREQ
SLEEP
DTACK
Name
STOP
TXRX
STOP
W
7
0
Stop Communication Processing Bit. (slave mode only)
This bit always reads as 0.
0: No effect.
1: Block the processing of LIN communications until the next SYNC BREAK signal.
Sleep Mode Bit. (slave mode only)
0: Wake the device after receiving a Wakeup interrupt.
1: Put the device into sleep mode after receiving a Sleep Mode frame or a bus idle
timeout.
Transmit / Receive Selection Bit.
0: Current frame is a receive operation.
1: Current frame is a transmit operation.
Data Acknowledge Bit. (slave mode only)
Set to 1 after handling a data request interrupt to acknowledge the transfer. The bit
will automatically be cleared to 0 by the LIN controller.
Reset Interrupt Bit.
This bit always reads as 0.
0: No effect.
1: Reset the LININT bit (LIN0ST.3).
Reset Error Bit.
This bit always reads as 0.
0: No effect.
1: Reset the error bits in LIN0ST and LIN0ERR.
Wakeup Request Bit.
Set to 1 to terminate sleep mode by sending a wakeup signal. The bit will automati-
cally be cleared to 0 by the LIN controller.
Start Request Bit. (master mode only)
1: Start a LIN transmission. This should be set only after loading the identifier, data
length and data buffer if necessary.
The bit is reset to 0 upon transmission completion or error detection.
SLEEP
R/W
6
0
TXRX
R/W
5
0
DTACK
R/W
Rev. 1.2
4
0
Function
RSTINT
W
3
0
RSTERR
W
2
0
WUPREQ
R/W
1
0
STREQ
R/W
0
0