SC28L202A1DGG,118 NXP Semiconductors, SC28L202A1DGG,118 Datasheet - Page 14

• Manufacturer Part Number: SC28L202A1DGG,118
• Description: IC UART DUAL W/FIFO 56-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L202A1DGG,118

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 56-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935276109118; SC28L202A1DGG-T; SC28L202A1DGG-T

Philips Semiconductors
I/O Ports
Eight I/O ports are ‘loosely’ provided for each channel. They may be
programmed to be inputs or outputs. The input circuits are always
active whether programmed as and input or an output. In general a
2-bit code in the I/OPCR (I/O Port Control Register) controls what
function these pins will present. All I/O ports default to high
impedance input state on power up. All 16 I/O pins have a small
pull-up ‘resistor’ that provides approximately 5 A current.
When calling software written for legacy two channel UARTs
manufactured by Philips (Signetics), be sure I/O pins are set to
input where the legacy software expected an input. Declare I/O
pins as output where the legacy software expected an output.
Input Characteristics of the I/O ports
Eight I/O pins are provided for each channel. These pins are
configured individually to be inputs or outputs. As inputs they may
be used to bring external data to the bus, as clocks for internal
functions or external control signals. Each I/O pin has a ‘Change of
State’ detector. The change detectors are used to signal a change in
the signal level at the pin (Either 0-to-1 or 1-to-0 transitions). The
level change on these pins must be stable for 25 to 50 s (two
edges of the internally generated 38.4 kHz baud rate clock) before
the detectors will signal a valid change. These are typically used for
interface signals from modems to the DUART and from there to the
host.
Output Port of the I/O ports
The OPR, I/OPCR, MR, and CR registers may control the I/O pins
when configured as outputs. (For the control in the lower 16 position
address space the control register is the OPCR) Via appropriate
programming the pins of the output port may be configures as
another parallel port to external circuits, or they may represent
internal conditions of the UART. When this 8-bit port is used as a
general-purpose output port, the output port pins drive inverse logic
levels of the individual bits in the Output Port Register (OPR). The
OPR register is set and reset by writing to the SOPR and ROPR
addresses. (See the description of the SOPR and ROPR registers).
The output pins will drive the same data polarity of the OPR
registers. The I/OPCR (or the OPCR) register conditions these
output pins to be controlled by the OPR or by other signals in the
chip. Output ports are driven high on hardware reset.
UART Operation
Receiver and Transmitter
The Dual UART has two full duplex asynchronous
receiver/transmitters. The operating frequency for the receiver and
transmitter can be selected independently from the baud rate
generator, the counter, or from an external input. Registers that are
central to basic full-duplex operation are the mode registers (MR0,
MR1 and MR2), the clock select registers (RxCSR and TxCSR), the
command register (CR), the status register (SR), the transmit
holding register (TxFIFO), the receive holding register (RxFIFO),
interrupt status register (ISR) and interrupt mask register (IMR).
MR3 controls the automatic activity or the Xon/Xoff flow control,
Address recognition, multi-drop (‘9-bit’ mode) and general purpose
character recognition. Because MR3 does not exist in legacy
UARTs, these features should be disabled before legacy code is
loaded.
Transmitter Status Bits
The SR (Status Register, one per UART) contains two bits that show
the condition of the transmitter FIFO. These bits are TxRDY and Tx
Idle. TxRDY means the TxFIFO has space available for one or more
bytes; Tx Idle means The TxFIFO is completely empty and the last
stop bit has been completed—the transmitter is underrun. Tx Idle
2005 Nov 01
Dual UART
8
can not be active without TxRDY also being active. These two bits
will go active upon initial enabling of the transmitter.
The transmitter status bits are normally cleared by servicing the
interrupt condition they represent or by Tx reset or Tx disable
commands.
Transmission resumes and the Tx Idle bit is cleared when the CPU
loads at least one new character into the TxFIFO. The TxRDY will
not extinguish until the TxFIFO is completely full. The TxRDY bit will
always be active when the transmitter is enabled and there is at
lease one open position in the TxFIFO.
The transmitter is disabled by a hardware reset, a transmitter reset
in the command register or by the transmitter disable bit also in the
command register (CR). The transmitter must be explicitly enabled
via the CR before transmission can begin. Note that characters
cannot be loaded into the TxFIFO while the transmitter is disabled,
hence it is necessary to enable the transmitter and then load the
TxFIFO. It is not possible to load the TxFIFO and then enable the
transmission.
Note the difference between transmitter disable and transmitter
reset.
Either hardware or software may cause the reset action. When reset
the transmitter stops transmission immediately. The transmit data
output will be driven high, transmitter status bits set to zero and any
data remaining in the TxFIFO is effectively discarded.
The transmitter disable is controlled by the Tx Enable bit in the
command register. Setting this bit to zero will not stop the transmitter
immediately but will allow it to complete any tasks presently
underway. It is only when the last character in the TxFIFO and its
stop bit(s) have been transmitted that the transmitter will go to its
disabled state. While the transmitter enable/disable bit in the
command register is at zero the TxFIFO will not accept any more
characters and the Tx Idle and TxRDY bits of the status register set
to zero.
Transmission of ‘break’
Transmission of a break character is often needed as a
synchronizing condition in a data stream. The ‘break’ is defined as a
start bit followed by all zero data bits by a zero parity bit (if parity is
enabled) and a zero in the stop bit position. The forgoing is the
minimum time to define a break. The transmitter can be forced to
send a break (continuous low condition) by issuing a start break
command via the CR. Once the break starts, the TxD output
remains low until the host issues a command to ‘stop break’ via the
CR or the transmitter is issued a software or hardware reset. In
normal operation the break is usually much longer than one
character time.
1x and 16x modes, Transmitter
The transmitter clocking has two modes: 16x and 1x. Data is always
sent at the 1x rate. However the logic of the transmitter may be
operated with a clock that is 16 times faster than the data rate or at
the same rate as the data i.e. 1x. All clocks selected internally for
the transmitter (and the receiver) will be 16x clocks. Only when an
external clock is selected may the transmitter logic and state
machine operate in the 1x mode. The 1x or 16x clocking makes little
difference in transmitter operation. (This is not true in the receiver)
In the 16X-clock mode the transmitter will recognize a byte in the
TxFIFO within 1/16 to 2/16-bit time and thus begin transmission of
the start bit. In the 1x mode this delay may be up to 2 bit times.
Transmitter FIFO
The FIFO configuration of the as 28L202 is 256 8-bit words.
Interrupt levels may be set to any level within the FIFO size and may
be set differently for each FIFO. Logic associated with the FIFO
SC28L202
Product data sheet