SC16C654BIB64,151 NXP Semiconductors, SC16C654BIB64,151 Datasheet - Page 25
![IC UART QUAD W/FIFO 64-LQFP](/photos/6/98/69856/568-64-lqfp_sot314-2_sml.jpg)
SC16C654BIB64,151
Manufacturer Part Number
SC16C654BIB64,151
Description
IC UART QUAD W/FIFO 64-LQFP
Manufacturer
NXP Semiconductors
Type
IrDAr
Datasheet
1.SC16C654BIBS528.pdf
(58 pages)
Specifications of SC16C654BIB64,151
Number Of Channels
4, QUART
Package / Case
64-LQFP
Features
False-start Bit Detection
Fifo's
64 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
5 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.25 V
Supply Current
6 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.5 V or 3.3 V or 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-3647
935274936151
SC16C654BIB64-S
935274936151
SC16C654BIB64-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C654BIB64,151
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
SC16C654BIB64,151
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Philips Semiconductors
9397 750 14965
Product data sheet
7.1 Transmit (THR) and Receive (RHR) Holding Registers
7.2 Interrupt Enable Register (IER)
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7 to D0) to the
THR, providing that the THR or TSR is empty. The THR empty flag in the LSR register will
be set to a logic 1 when the transmitter is empty or when data is transferred to the TSR.
Note that a write operation can be performed when the THR empty flag is set
(logic 0 = FIFO full; logic 1 = at least one FIFO location available).
The serial receive section also contains an 8-bit Receive Holding Register (RHR).
Receive data is removed from the SC16C654B/654DB and receive FIFO by reading the
RHR register. The receive section provides a mechanism to prevent false starts. On the
falling edge of a start or false start bit, an internal receiver counter starts counting clocks
at the 16 clock rate. After 7
the start bit. At this time the start bit is sampled, and if it is still a logic 0 it is validated.
Evaluating the start bit in this manner prevents the receiver from assembling a false
character. Receiver status codes will be posted in the LSR.
The Interrupt Enable Register (IER) masks the interrupts from receiver ready, transmitter
empty, line status and modem status registers. These interrupts would normally be seen
on the INTA to INTD output pins in the 16 mode, or on wire-OR IRQ output pin in the
68 mode.
Table 9:
Bit
7
6
5
4
3
Symbol
IER[7]
IER[6]
IER[5]
IER[4]
IER[3]
Interrupt Enable Register bits description
Description
CTS interrupt.
RTS interrupt.
Xoff interrupt.
Sleep mode.
Modem Status Interrupt.
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt. The SC16C654B/654DB issues an
interrupt when the CTS pin transitions from a logic 0 to a logic 1.
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt. The SC16C654B/654DB issues an
interrupt when the RTS pin transitions from a logic 0 to a logic 1.
logic 0 = disable the software flow control, receive Xoff interrupt (normal
default condition)
logic 1 = enable the software flow control, receive Xoff interrupt. See
6.5 “Software flow control”
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode. See
logic 0 = disable the modem status register interrupt (normal default
condition)
logic 1 = enable the modem status register interrupt
Rev. 02 — 20 June 2005
1
2
clocks, the start bit time should be shifted to the center of
for details.
SC16C654B/654DB
Section 6.11 “Sleep mode”
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
for details.
Section
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