SC16C654BIB64,151 NXP Semiconductors, SC16C654BIB64,151 Datasheet - Page 30
![IC UART QUAD W/FIFO 64-LQFP](/photos/6/98/69856/568-64-lqfp_sot314-2_sml.jpg)
SC16C654BIB64,151
Manufacturer Part Number
SC16C654BIB64,151
Description
IC UART QUAD W/FIFO 64-LQFP
Manufacturer
NXP Semiconductors
Type
IrDAr
Datasheet
1.SC16C654BIBS528.pdf
(58 pages)
Specifications of SC16C654BIB64,151
Number Of Channels
4, QUART
Package / Case
64-LQFP
Features
False-start Bit Detection
Fifo's
64 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
5 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.25 V
Supply Current
6 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
2.5 V or 3.3 V or 5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-3647
935274936151
SC16C654BIB64-S
935274936151
SC16C654BIB64-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C654BIB64,151
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
SC16C654BIB64,151
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Philips Semiconductors
9397 750 14965
Product data sheet
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by writing the
appropriate bits in this register.
Table 15:
Bit
7
6
5
4
3
2
1:0
Line Control Register bits description
Symbol
LCR[7]
LCR[6]
LCR[5]
LCR[4]
LCR[3]
LCR[2]
LCR[1:0]
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Rev. 02 — 20 June 2005
Description
Divisor latch enable. The internal baud rate counter latch and Enhance
Feature mode enable.
Set break. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0 state).
This condition exists until disabled by setting LCR[6] to a logic 0.
Set parity. If the parity bit is enabled, LCR[5] selects the forced parity
format. Programs the parity conditions; see
Even parity. If the parity bit is enabled with LCR[3] set to a logic 1,
LCR[4] selects the even or odd parity format.
Parity enable. Parity or no parity can be selected via this bit.
Stop bits. The length of stop bit is specified by this bit in conjunction with
the programmed word length; see
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received; see
logic 0 = divisor latch disabled (normal default condition)
logic 1 = divisor latch and enhanced feature register enabled
logic 0 = no TX break condition (normal default condition)
logic 1 = forces the transmitter output (TX) to a logic 0 for alerting the
remote receiver to a line break condition
logic 0 = parity is not forced (normal default condition)
LCR[5] = logic 1 and LCR[4] = logic 0: parity bit is forced to a logical 1
for the transmit and receive data
LCR[5] = logic 1 and LCR[4] = logic 1: parity bit is forced to a logical 0
for the transmit and receive data
logic 0 = odd parity is generated by forcing an odd number of logic 1s
in the transmitted data. The receiver must be programmed to check
the same format (normal default condition).
logic 1 = even parity is generated by forcing an even number of
logic 1s in the transmitted data. The receiver must be programmed to
check the same format.
logic 0 = no parity (normal default condition)
logic 1 = a parity bit is generated during the transmission, receiver
checks the data and parity for transmission errors
logic 0 or cleared = default condition
logic 0 or cleared = default condition
SC16C654B/654DB
Table
Table
18.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
17.
Table
16.
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