SC16C652IB48,151 NXP Semiconductors, SC16C652IB48,151 Datasheet - Page 8

• Manufacturer Part Number: SC16C652IB48,151
• Description: IC UART DUAL W/FIFO 48-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C652IB48,151

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 32 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Package Type: LQFP
• Operating Supply Voltage (max): 5.5V
• Mounting: Surface Mount
• Pin Count: 48
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3277; 935270032151; SC16C652IB48-S

Philips Semiconductors
9397 750 11634
Product data
6.2 Internal registers
6.3 FIFO operation
The SC16C652 provides two sets of internal registers (A and B) consisting of
12 registers each for monitoring and controlling the functions of each channel of the
UART. These registers are shown in
holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO
control register (FCR), line status and control registers (LCR/LSR), modem status
and control registers (MCR/MSR), programmable data rate (clock) control registers
(DLL/DLM), and a user accessible scratchpad register (SPR).
Table 4:
[1]
[2]
[3]
The 32-byte transmit and receive data FIFOs are enabled by the FIFO Control
Register bit-0 (FCR[0]). With 16C2550 devices, the user can set the receive trigger
level, but not the transmit trigger level. The SC16C652 provides independent trigger
levels for both receiver and transmitter. To remain compatible with SC16C2550, the
transmit interrupt trigger level is set to 16 following a reset. It should be noted that the
user can set the transmit trigger levels by writing to the FCR register, but activation
will not take place until EFR[4] is set to a logic 1. The receiver FIFO section includes
a time-out function to ensure data is delivered to the external CPU. An interrupt is
generated whenever the Receive Holding Register (RHR) has not been read
following the loading of a character or the receive trigger level has not been reached.
A2
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)
0
0
0
0
1
1
1
1
Baud rate register set (DLL/DLM)
0
0
Enhanced register set (EFR, Xon/off 1-2)
0
1
1
1
1
These registers are accessible only when LCR[7] is a logic 0.
These registers are accessible only when LCR[7] is a logic 1.
Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to
‘BF(HEX)’.
A1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
Internal registers decoding
A0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
Rev. 04 — 20 June 2003
READ mode
Receive Holding Register
Interrupt Status Register
Line Status Register
Modem Status Register
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
Dual UART with 32 bytes of transmit and receive FIFOs
[2]
Table
[3]
4. The UART registers function as data
WRITE mode
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
n/a
n/a
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C652
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