SC16C654DIB64,151 NXP Semiconductors, SC16C654DIB64,151 Datasheet - Page 31
![IC UART QUAD W/FIFO 64-LQFP](/photos/6/98/69856/568-64-lqfp_sot314-2_sml.jpg)
SC16C654DIB64,151
Manufacturer Part Number
SC16C654DIB64,151
Description
IC UART QUAD W/FIFO 64-LQFP
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C654DIB64151.pdf
(52 pages)
Specifications of SC16C654DIB64,151
Number Of Channels
4, QUART
Fifo's
64 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3281
935270050151
SC16C654DIB64-S
935270050151
SC16C654DIB64-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C654DIB64,151
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
9397 750 11617
Product data
7.10 Enhanced Feature Register (EFR)
7.9 Scratchpad Register (SPR)
Table 21:
[1]
The SC16C654/654D provides a temporary data register to store 8 bits of user
information.
Enhanced features are enabled or disabled using this register.
Bits 0 through 4 provide single or dual character software flow control selection.
When the Xon1 and Xon2 and/or Xoff1 and Xoff2 modes are selected, the double
8-bit words are concatenated into two sequential numbers.
Table 22:
Bit
1
0
Bit
7
6
Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated.
Symbol
MSR[1]
MSR[0]
Symbol
EFR[7]
EFR[6]
Modem Status Register bits description
Enhanced Feature Register bits description
Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder
Rev. 04 — 19 June 2003
Description
Description
Auto CTS. Automatic CTS Flow Control.
Auto RTS. Automatic RTS may be used for hardware flow control by
enabling EFR[6]. When Auto RTS is selected, an interrupt will be
generated when the receive FIFO is filled to the programmed trigger
level and RTS will go to a logic 1 at the next trigger level. RTS will return
to a logic 0 when data is unloaded below the next lower trigger level
(Programmed trigger level -1). The state of this register bit changes with
the status of the hardware flow control. RTS functions normally when
hardware flow control is disabled.
DSR
CTS
Logic 0 = No DSR change (normal default condition).
Logic 1 = The DSR input to the SC16C654/654D has changed state
since the last time it was read. A Modem Status Interrupt will be
generated.
Logic 0 = No CTS change (normal default condition).
Logic 1 = The CTS input to the SC16C654/654D has changed state
since the last time it was read. A Modem Status Interrupt will be
generated.
Logic 0 = Automatic CTS flow control is disabled (normal default
condition).
Logic 1 = Enable Automatic CTS flow control. Transmission will stop
when CTS goes to a logical 1. Transmission will resume when the CTS
pin returns to a logical 0.
Logic 0 = Automatic RTS flow control is disabled (normal default
condition).
Logic 1 = Enable Automatic RTS flow control.
[1]
[1]
…continued
SC16C654/654D
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
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