SC16C2550IB48,128 NXP Semiconductors, SC16C2550IB48,128 Datasheet - Page 16
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SC16C2550IB48,128
Manufacturer Part Number
SC16C2550IB48,128
Description
IC DUART SOT313-2
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C2550IN40112.pdf
(46 pages)
Specifications of SC16C2550IB48,128
Features
2 Channels
Number Of Channels
2, DUART
Fifo's
16 Byte
Voltage - Supply
3.5 V ~ 4.5 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
48-LQFP
Transmit Fifo
16Byte
Receive Fifo
16Byte
Transmitter And Receiver Fifo Counter
Yes
Data Rate
5Mbps
Package Type
LQFP
Operating Supply Voltage (max)
5.5V
Mounting
Surface Mount
Pin Count
48
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935270020128
SC16C2550IB48-T
SC16C2550IB48-T
SC16C2550IB48-T
SC16C2550IB48-T
Philips Semiconductors
7. Register descriptions
Table 7:
Shaded bits are only accessible when EFR[4] is set.
[1]
[2]
[3]
[4]
9397 750 11621
Product data
A2
General Register Set
0
0
0
0
0
0
1
1
1
1
Special Register Set
0
0
Enhanced Register Set
0
1
1
1
1
The value shown in represents the register’s initialized HEX value; X = n/a.
Accessible only when LCR[7] is logic 0.
Baud rate registers accessible only when LCR[7] is logic 1.
Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BF
A1
0
0
0
1
1
1
0
0
1
1
0
0
1
0
0
1
1
A0
0
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
SC16C2550 internal registers
Register Default
RHR
THR
IER
FCR
ISR
LCR
MCR
LSR
MSR
SPR
DLL
DLM
EFR
Xon-1
Xon-2
Xoff-1
Xoff-2
[3]
[2]
[4]
XX
XX
00
00
01
00
00
60
X0
FF
XX
XX
00
00
00
00
00
Table 7
assigned bit functions are more fully defined in
[1]
details the assigned bit functions for the SC16C2550 internal registers. The
Bit 7
bit 7
bit 7
CTS
interrupt
RCVR
trigger
(MSB)
FIFOs
enabled
divisor
latch
enable
0
FIFO
data
error
CD
bit 7
bit 7
bit 15
Auto
CTS
bit 7
bit 15
bit 7
bit 15
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA
Bit 6
bit 6
bit 6
RTS
interrupt
RCVR
trigger
(LSB)
FIFOs
enabled
set break set parity even
IR
enable
THR and
TSR
empty
RI
bit 6
bit 6
bit 14
Auto
RTS
bit 6
bit 14
bit 6
bit 14
Rev. 03 — 19 June 2003
Bit 5
bit 5
bit 5
Xoff
interrupt
reserved
0
INT
priority
bit 4
0
THR
empty
DSR
bit 5
bit 5
bit 13
Special
char.
select
bit 5
bit 13
bit 5
bit 13
Bit 4
bit 4
bit 4
Sleep
mode
reserved
0
INT
priority
bit 3
parity
loop back OP2/INT
break
interrupt
CTS
bit 4
bit 4
bit 12
Enable
IER[4-7],
ISR[4,5],
FCR[4,5],
MCR[5-7]
bit 4
bit 12
bit 4
bit 12
Section 7.1
Bit 3
bit 3
bit 3
modem
status
interrupt
DMA
mode
select
INT
priority
bit 2
parity
enable
enable
framing
error
bit 3
bit 3
bit 11
Cont-3
Tx, Rx
Control
bit 3
bit 11
bit 3
bit 11
CD
Hex
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
’.
Bit 2
bit 2
bit 2
receive
line
status
interrupt
XMIT
FIFO
reset
INT
priority
bit 1
stop bits word
(OP1)
parity
error
bit 2
bit 2
bit 10
Cont-2
Tx, Rx
Control
bit 2
bit 10
bit 2
bit 10
RI
through
SC16C2550
encoder/decoder
Bit 1
bit 1
bit 1
transmit
holding
register
interrupt
RCVR
FIFO
reset
INT
priority
bit 0
length
bit 1
RTS
overrun
error
bit 1
bit 1
bit 9
Cont-1
Tx, Rx
Control
bit 1
bit 9
bit 1
bit 9
Section
DSR
7.11.
Bit 0
bit 0
bit 0
receive
holding
register
FIFOs
enable
INT
status
word
length
bit 0
DTR
receive
data
ready
bit 0
bit 0
bit 8
Cont-0
Tx, Rx
Control
bit 0
bit 8
bit 0
bit 8
CTS
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